• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.103-106
• /
• 2003

An oscillatory neural network circuit has been designed and fabricated in an 0.5 ${\mu}{\textrm}{m}$ double poly CMOS technology. The proposed oscillatory neural network consists of 3 neural oscillator cells with excitatory synapses and a neural oscillator cell with inhibitory synapse. Simulations of a network of oscillators demonstrate cooperative computation. Measurements of the fabricated chip in condition of $\pm$ 2.5 V power supply is shown.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.153-156
• /
• 2001

This paper describes a 12-bit high speed pipeline CMOS A/D converter. The A/D converter simulated the 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. The results show DNL and INL of $\pm$0.5LSB and $\pm$1.0LSB, conversion rate of 100Msamples/s, and power dissipation of 500㎽ with a power supply of 3.3V

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.693-696
• /
• 1999

This paper presents an analysis of the chaotic behavior in the discrete-time chaotic generator fabricated by CMOS technology. An approximated empirical equation is extracted from the measurement data of a nonlinear function block. Then the bifurcation diagram and Lyapunov exponent and time waveforms and frequency responses of the chaotic generator are calculated and simulated. And results of experiments in the chaotic circuit with the $\pm$2.5V power supply and clock rate of 10KHz are shown, and analysed.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.3
• /
• pp.189-192
• /
• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• Proceedings of the IEEK Conference
• /
• 2000.06e
• /
• pp.61-64
• /
• 2000

This paper describes a RF Down-Conversion Mixer for mobile communication systems. This circuit achieves low voltage operation and low power consumption by reducing stacked devices of conventional gilbert cell mixer. In order to reduce stacked devices, we use source-follower structure. The proposed RF Down-Conversion mixer operates up to 1.85GHz at 1.5V power supply with 0.25um CMOS technology and consumes 2.2mA.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.3
• /
• pp.153-166
• /
• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• 한국정보통신설비학회:학술대회논문집
• /
• 2006.08a
• /
• pp.179-182
• /
• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.52 no.8
• /
• pp.330-334
• /
• 2003

A Temperature sensor system in which the digital output signal is proportional to the operating temperature is designed. The temperature sensor system is designed by using BiCMOS technology and consists of temperature sensor, voltage-to-frequency converter and counter. The proposed temperature sensor system has error less than $1^{\circ}C$ in the temperature range $-25^{\circ}C$ to $55^{\circ}C$.

• Proceedings of the Optical Society of Korea Conference
• /
• 2001.02a
• /
• pp.180-181
• /
• 2001

이 논문은 채널당 1Gbps로 동작하는 10채널 광 수신기를 0.25$mu extrm{m}$ CMOS공정을 이용하여 설계한 것이다. 광 수신기는 크게 2부분으로 나눠지는데 첫 번째 부분은 입력된 전류 신호를 전압 신호로 변환시켜주는 역할을 하는 트랜스임피던스 전치증폭기이고, 다음 부분은 원하는 디지털 레벨로 풀스윙 할 수 있도록 하는 후치증폭기이다. 전치증폭기의 출력 전압은 스윙폭에 무관하게 그 다음 단에서 적당한 디지털 레벨 데이터로 변환되어야한다. (중략)

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.190-197
• /
• 2011

This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90-nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm ${\times}$ 0.69 mm including the DC and RF pads.