• Title/Summary/Keyword: CMOS inverter

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Design of a Low-Voltage $Constant-g_m$ Rail-to-Rail CMOS Op-amp (저전압 $Constant-g_m$ Rail-to-Rail CMOS 증폭회로 설계)

  • 이태원;이경일;오원석;박종태;유창근
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.2
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    • pp.22-28
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    • 1998
  • A $g_m$-control technique using a new electronic zener diode (EZD) for CMOS rail-torail input stages is presented. A regulated CMOS inverter is used as an EZD to obtain a constant-$g_m$ input stage. The turn-off characteristic of the proposed EZD is better than that of the existing EZD using two complementarey diodes, and thus, better $g_m$-control can be achieved. With this input stage, a 3V constant-$g_m$ rail-to-rail CMOS op-amp has been designed and fabricated using a $0.8\mu\extrm{m}$single-poly, double-metal CMOS process. Measurements results show that the $g_m$ variation is about 6% over the entire input common-mode range, and the op-amp has a dc gain of 88dB and a unity-gain frequency of 4MHz for $C_L=20pF, R_L=10k\Omega$

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A 1V Analog CMOS Front-End for Cardiac Pacemaker Applications (심장박동 조절장치를 위한 1V 아날로그 CMOS 전단 처리기)

  • Chae, Young-Cheol;Lee, Jeong-Whan;Lee, In-Hee;Han, Gun-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.45-51
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    • 2009
  • A low-voltage, low-power analog CMOS front-end for a cardiac pacemaker is proposed. The circuits include a 4th order switched-capacitor (SC) filter with a passband of 80-120 Hz and a SC variable gain amplifier whose control range is from 0 to 24-dB with 0.094 dB step. An inverter-based switched-capacitor circuit technique is used for low-voltage operation and ultra-low power consumption, and correlated double sampling technique is used for reducing the finite gain effect of an inverter. The proposed circuit has been designed in a $0.35-{\mu}m$ CMOS process, and it achieves 80-dB SFDR at 5-kHz sampling frequency. The power consumption is only 330 nW at 1-V power supply.

Multi-output VC-TCXO having CMOS inverter for WCDMA(UMTS) (CMOS 인버터를 갖는 WCDMA(UMTS)용 다중출력 VC-TCXO)

  • Jeong Chan-Yong;Lee Hai-Young
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.8 s.350
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    • pp.6-12
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    • 2006
  • Recently, according to the rapid development of mobile system, the development of relative mobile components has been required, and especially, with the miniaturization of mobile component, the complex with nearby components has been progressed. In this paper, multi-output VC-TCXO (Voltage Controlled-Temperature Compensated Crystal Oscillator) for WCDMA integrates the additional CMOS inverter, so it can be the normal clipped sinewave output and additional CMOS output, and also it can be satisfied the VC-TCXO's requirements for WCDMA system. And the important characteristics of reference oscillator, like phase noise and frequency short term stability, are satisfied with WCDMA(UMTS) system's requirement In this paper, however, 25MHz is used for reference frequency, similarly and practically, we think that it can be used from 10MHz to 40MHz.

Fabrication, Mesurement and Evaluation of Silicon-Gate n-well CMOS Devices (실리콘 게이트 n-well CMOS 소자의 제작, 측정 및 평가)

  • Ryu, Jong-Seon;Kim, Gwang-Su;Kim, Bo-U
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.21 no.5
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    • pp.46-54
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    • 1984
  • A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

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Implementation of Logic Gates Using Organic Thin Film Transistor for Gate Driver of Flexible Organic Light-Emitting Diode Displays (유기 박막 트랜지스터를 이용한 유연한 디스플레이의 게이트 드라이버용 로직 게이트 구현)

  • Cho, Seung-Il;Mizukami, Makoto
    • The Journal of the Korea institute of electronic communication sciences
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    • v.14 no.1
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    • pp.87-96
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    • 2019
  • Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

The Design of CMOS DDA and DDA differential integrator (CMOS DDA와 DDA 차동 적분기의 설계)

  • 유철로;김동용;윤창훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.18 no.4
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    • pp.602-610
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    • 1993
  • The DDA of new active element and the DDA differential integrator are designed. The DDA can be improved matching problems of external elements in op-amp application circuits. The design of DDA is used the transconductance element, differential pair and $2{\mu}m$ design rule. In order to evaluate the performance of the CMOS DDA, we simulated the DDA voltage inverter and the DDA level shifter using the designed CMOS DDA. Furthermore, the grounded resistor and the differential integrator is designed using the CMOS DDA and we found that its characteristics are agreed to OP-AMP differential integrator's. We performed the layout of the CMOS DDA and DDA differential integrator with MOSIS $2{\mu}m$ CMOS technology.

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Design of a Inverter-Based 3rd Order ΔΣ Modulator Using 1.5bit Comparators (1.5비트 비교기를 이용한 인버터 기반 3차 델타-시그마 변조기)

  • Choi, Jeong Hoon;Seong, Jae Hyeon;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.7
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    • pp.39-46
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    • 2016
  • This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

A Study on SOI-like-bulk CMOS Structure Operating in Low Voltage with Stability (저전압동작에 적절한 SOI-like-bulk CMOS 구조에 관한 연구)

  • Son, Sang-Hee;Jin, Tae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.6
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    • pp.428-435
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    • 1998
  • SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

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the Design Methodology of Minimum-delay CMOS Buffer Circuits (최소 지연시간을 갖는 CMOS buffer 회로의 설계 기법)

  • 강인엽;송민규;이병호;김원찬
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.5
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    • pp.509-521
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    • 1988
  • In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

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An Implementation of the switch-Level Fault Simulator for CMOS Circuits with a Gate-to-Drain/Source short Fault (게이트와 드레인/소오스 단락결함을 갖는 CMOS 회로의 스위치 레벨 결함 시뮬레이터 구현)

  • 정금섭;전흥우
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.4
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    • pp.116-126
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    • 1994
  • In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.

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