• Title/Summary/Keyword: CMOS image Sensor

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Developing a CIS Camera Interface for Embedded Systems (임베디드 시스템에서 CIS 카메라 인터페이스의 구현)

  • Lee, Wan-Su;Oh, Sam-Kwan;Hwang, Hee-Yeung;Roh, Young-Sub
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.8 no.3
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    • pp.513-521
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    • 2007
  • Recently, camera function is one of the most primary functions out of the multimedia capabilities in the small mobile terminals. But, it has been difficult for implementing embedded devices with low cost because of not supporting camera interface in many SoCs. Thus, this paper presents a method of supporting camera function with ease for embedded devices which has not camera interface. For this purpose, the interface is implemented for a CMOS image sensor. The method is also provided that CIS(CMOS Image Sensor) is supported in the embedded system by programming the device driver.

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Algorithm of Optical Camera Communications Using Rolling-Shutter Effect (롤링셔터 효과를 이용한 광학 카메라통신 알고리즘)

  • Lee, Jungho;Kim, Nayeong;Ju, MinChul;Park, Youngil
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.4
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    • pp.454-460
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    • 2016
  • Unlike conventional visible light communications (VLC) adopting photo detectors (PD), optical camera communications (OCC) employs cameras in detecting the transmitted data. Especially, the data rate of OCC can be enhanced by using the principle of rolling-shutter, which is the operating scheme of a CMOS image sensor. In this study, we consider a novel OCC system for high-speed real time video processing to transmit high speed data from LED and to acquire image utilizing rolling-shutter effect of CMOS image sensor. Also, we demonstrate the improved performance of proposed system using a test-bed.

Dual-Sensitivity Mode CMOS Image Sensor for Wide Dynamic Range Using Column Capacitors

  • Lee, Sanggwon;Bae, Myunghan;Choi, Byoung-Soo;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.26 no.2
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    • pp.85-90
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    • 2017
  • A wide dynamic range (WDR) CMOS image sensor (CIS) was developed with a specialized readout architecture for realizing high-sensitivity (HS) and low-sensitivity (LS) reading modes. The proposed pixel is basically a three-transistor (3T) active pixel sensor (APS) structure with an additional transistor. In the developed WDR CIS, only one mode between the HS mode for relatively weak light intensity and the LS mode for the strong light intensity is activated by an external controlling signal, and then the selected signal is read through each column-parallel readout circuit. The LS mode is implemented with the column capacitors and a feedback structure for adjusting column capacitor size. In particular, the feedback circuit makes it possible to change the column node capacitance automatically by using the incident light intensity. As a result, the proposed CIS achieved a wide dynamic range of 94 dB by synthesizing output signals from both modes. The prototype CIS is implemented with $0.18-{\mu}m$ 1-poly 6-metal (1P6M) standard CMOS technology, and the number of effective pixels is 176 (H) ${\times}$ 144 (V).

Design of Efficient Flicker Detector for CMOS Image Sensor (CMOS Image sensor 를 위한 효과적인 플리커 검출기 설계)

  • Lee, Pyeong-Woo;Lee, Jeong-Guk;Kim, Chae-Sung
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.739-742
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    • 2005
  • In this paper, an efficient detection algorithm for the flicker, which is caused by mismatching between light frequency and exposure time at CMOS image sensor (CIS), is proposed. The flicker detection can be implemented by specific hardware or complex signal processing logic. However it is difficult to implement on single chip image sensor, which has pixel, CDS, ADC, and ISP on a die, because of limited die area. Thus for the flicker detection, the simple algorithm and high accuracy should be achieved on single chip image sensor,. To satisfy these purposes, the proposed algorithm organizes only simple operation, which calculates the subtraction of horizontal luminance mean between continuous two frames. This algorithm was verified with MATLAB and Xilinx FPGA, and it is implemented with Magnachip 0.18 standard cell library. As a result, the accuracy is 95% in average on FPGA emulation and the consumed gate count is about 7,500 gates (@40MHz) for implementation using Magnachip 0.18 process.

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Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC (10-bit Two-Step Single Slope A/D 변환기를 이용한 고속 CMOS Image Sensor의 설계)

  • Hwang, Inkyung;Kim, Daeyun;Song, Minkyu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.64-69
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    • 2013
  • In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

Measurement of noise characteristics of an image sensor (화상센서의 잡음 특성 측정)

  • Lee, Tae-Kyoung;Hahn, Jae-Won
    • Transactions of the Society of Information Storage Systems
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    • v.5 no.2
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    • pp.89-95
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    • 2009
  • We setup the system to measure the noise characteristics of the 5M complementary metal-oxide semiconductor (CMOS) image sensor by generic measurement indicator of Standard mobile imaging architecture (SMIA) which is one of internal standard of mobile imaging architecture. To evaluate the effect of environment and setting parameters, such as temperature and integration time, we measure the variation of the dark signal, dynamic range and fixed pattern noise of image sensor. We also detect the number of defective pixels and cluster defects defined as adjacent single defect pixels at 5M CMOS image sensor. Then, we find the existence of some cluster defects in experiment, which are not expected in calculation.

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Design of a CMOS Image Sensor Based on a Low Power Single-Slope ADC (저전력 Single-Slope ADC를 사용한 CMOS 이미지 센서의 설계)

  • Kwon, Hyuk-Bin;Kim, Dae-Yun;Song, Min-Kyu
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.2
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    • pp.20-27
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    • 2011
  • A CMOS Image Sensor(CIS) mounted on mobile appliances always needs a low power consumption because of the battery life cycle. In this paper, we propose novel power reduction techniques such as a data flip-flop circuit with leakage current elimination, a low power single slope A/D converter with a novel comparator, and etc. Based on 0.13um CMOS process, the chip satisfies QVGA resolution($320{\times}240$ pixels) whose pitch is 2.25um and whose structure is 4-Tr active pixel sensor. From the experimental results, the ADC in the middle of CIS has a 10-b resolution, the operating speed of CIS is 16 frame/s, and the power dissipation is 25mW at 3.3V(Analog)/1.8V(Digital) power supply. When we compare the proposed CIS with conventional ones, the power consumption is reduced approximately by 22% in sleep mode, 20% in operating mode.

Dynamic Range Extension of CMOS Image Sensor with Column Capacitor and Feedback Structure (컬럼 커패시터와 피드백 구조를 이용한 CMOS 이미지 센서의 동작 범위 확장)

  • Lee, Sanggwon;Jo, Sung-Hyun;Bae, Myunghan;Choi, Byoung-Soo;Kim, Heedong;Shin, Eunsu;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.24 no.2
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    • pp.131-136
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    • 2015
  • This paper presents a wide dynamic range complementary metal oxide semiconductor (CMOS) image sensor with column capacitor and feedback structure. The designed circuit has been fabricated by using $0.18{\mu}m$ 1-poly 6-metal standard CMOS technology. This sensor has dual mode operation using combination of active pixel sensor (APS) and passive pixel sensor (PPS) structure. The proposed pixel operates in the APS mode for high-sensitivity in normal light intensity, while it operates in the PPS mode for low-sensitivity in high light intensity. The proposed PPS structure is consisted of a conventional PPS with column capacitor and feedback structure. The capacitance of column capacitor is changed by controlling the reference voltage using feedback structure. By using the proposed structure, it is possible to store more electric charge, which results in a wider dynamic range. The simulation and measurement results demonstrate wide dynamic range feature of the proposed PPS.

Fabrication of Infrared Filters for Three-Dimensional CMOS Image Sensor Applications

  • Lee, Myung Bok
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.6
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    • pp.341-344
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    • 2017
  • Infrared (IR) filters were developed to implement integrated three-dimensional (3D) image sensors that are capable of obtaining both color image and depth information at the same time. The combination of light filters applicable to the 3D image sensor is composed of a modified IR cut filter mounted on the objective lens module and on-chip filters such as IR pass filters and color filters. The IR cut filters were fabricated by inorganic $SiO_2/TiO_2$ multilayered thin-film deposition using RF magnetron sputtering. On-chip IR pass filters were synthetized by dissolving various pigments and dyes in organic solvents and by subsequent patterning with photolithography. The fabrication process of the filters is fairly compatible with the complementary metal oxide semiconductor (CMOS) process. Thus, the IR cut filter and IR pass filter combined with conventional color filters are considered successfully applicable to 3D image sensors.