• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.15-19
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• 2011

We have proposed a maximum power point tracking (MPPT) circuit for thermoelectric generator (TEG) using a Boost converter. The key point of the proposed MPPT circuit is that the duty ratio of the boost converter automatically moves to Maximum Power Point by comparing of consecutive sampling voltage using two comparators. From the simulation results, we showed that the proposed circuit can find the maximum power point within 2 CLK periods and to generate optimal PWM signal within 3 CLK periods. The proposed MPPT circuit was designed by using a CMOS 0.18 um process, and it is now on the fabrication.

• Journal of Sensor Science and Technology
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• v.31 no.6
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• pp.366-370
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• 2022

A 12 ㎛ pixel-sized 360 × 240 microbolometer focal plane array (MBFPA) was fabricated using a complementary metaloxide-semiconductor (CMOS)-compatible process. To release the MBFPA membrane, an amorphous carbon layer (ACL) processed at a low temperature (<400 ℃) was deposited as a sacrificial layer. The thermal time constant of the MBFPA was improved by using serpentine legs and controlling the thickness of the SiNx layers at 110, 130, and 150 nm on the membrane, with response times of 6.13, 6.28, and 7.48 msec, respectively. Boron-doped amorphous Si (a-Si), which exhibits a high-temperature coefficient of resistance (TCR) and CMOS compatibility, was deposited on top of the membrane as an IR absorption layer to provide heat energy transformation. The structural stability of the thin SiNx membrane and serpentine legs was observed using field-emission scanning electron microscopy (FE-SEM). The fabrication yield was evaluated by measuring the resistance of a representative pixel in the array, which was in the range of 0.8-1.2 Mohm (as designed). The yields for SiNx thicknesses of SiNx at 110, 130, and 150 nm were 75, 86, and 86%, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1228-1238
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• 2012

In this paper, we design, fabricate and measure two kinds of high-frequency packages for K-band CMOS FMCW radar chips using RF via structures. The packages are fabricated with the conventional PCB process and LTCC process. The design centering of the packages is performed at 24 GHz and impedance variation caused by the wire bonding and RF via structure is fully evaluated using 3D electromagnetic simulation. The RF via structure with characteristic impedance of $50{\Omega}$ is used to reduce impedance mismatch loss. Two kinds of test packages with back-to-back connected RF paths are fabricated and measured for the design verification of the PCB-based package and LTCC package. Their measured results show an insertion loss of less than 0.4 dB at 24 GHz and less than 0.5 dB for 20~29 GHz. The measured return loss is less than -13 dB for the PCB-based package and less than -15 dB for the LTCC package in the frequency band, but the return loss of the package itself is predicted to be better than that of the test package by about 5 dB, because the ripples of the back-to-back connection typically degrade the return loss by 5 dB or more.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.55 no.1
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• pp.26-30
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• 2006

For the purpose of developing capacitive humidity sensor having interdigital electrodes, interdigital electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thickness. For the development of ASIC, switched capacitor signal processing circuits for capacitive humidity sensor were designed and simulated by Cadence using $0.25{\mu}m$ CMOS process parameters. The signal processing circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control. The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is $0.4%R.H./^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of $3%R.H.{\sim}98%R.H.$. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigital electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.3
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• pp.144-148
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• 2001

For the purpose of developing capacitive humidity sensor having interdigit electrodes, interdigit electrode was modeled and simulated to obtain capacitance and sensitivity as a function of geometric parameters like the structural gap and thichness. For the development of ASIC, switched capacitor signal conditioning circuits for capacitive humidity sensor were designed and simulated by cadence using 0.25um CMOS process parameters. The signal conditioning circuits are composed of amplifier for voltage gain control, and clock generator for sensor driving and switch control The characteristics of the fabricated sensors are; 1) sensitivity is 9fF/%R.H., 2) temperature coefficient of offset(TCO) is 0.4%R.H./$^{\circ}C$, 3) nonlinearity is 1.2%FS, 4) hysteresis is 1.5%FS in humidity range of 3%R.H. ${\sim}$ 98%R.H.. The response time is 50 seconds in adsorption and 70 seconds in desorption. Fabricated process used in this capacitive humidity sensor having interdigit electrode are just as similar as conventional IC process technology. Therefore this can be easily mass produced with low cost, simple circuit and utilized in many applications for both industrial and environmental measurement and control system, such as monitoring system of environment, automobile, displayer, IC process room, and laboratory etc..

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.278-283
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• 2013

This paper presents a design and fabrication of 0.5 V two stage operational amplifier. The proposed operational amplifier utilizes body-driven differential input stage and self-cascode current mirror structure. Cadence Virtuoso is used for layout and the layout data is verified by LVS through Mentor Calibre. The proposed two stage operational amplifier is fabricated using $0.13{\mu}m$ CMOS process and operation at 0.5 V is confirmed. Measured low frequency small signal gain of operational amplifier is 50 dB, power consumption is $29{\mu}W$ and chip area is $75{\mu}m{\times}90{\mu}m$.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.295-298
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• 2003

Reflective mode liquid crystal on silicon (LCoS) microdisplay is the major technology that can produce extremely high-resolution displays. A very large number of pixels can be packed onto the CMOS circuit with integrated drivers that can be projected to any size screen. Large size direct-view thin film transistor (TFT) LCDs becomes very difficult to make and to drive as the information content increases. However, the existing LC alignment technology for the LCoS cell fabrication is still the mechanical rubbing method, which is prone to have minor defects that are not visible normally but can be detrimental if projected to a large screen. In this paper, application of photo-alignment to LCoS fabrication is presented. The alignment is done by three-step exposure process. A MTN $90^{\circ}$ mode is chose as to evaluate the performance of this technique. The comparison with rubbing mode shows the performance of photo-alignment is comparable and even better in some aspect, such as sharper RVC curve and higher contrast ratio.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.65-73
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• 1986

Experiment have been conducted about thin oxide characteristics according to O2/N2 ratio needed for EEPROM cell fabrication. As a result, we think that there is no problem even if we grow oxide layer with large O2/N2 ratio and short exidation time and when the water is implated by As before oxidation, the oxide breakdown field is about IMV/cm lower than that is not implanted. Especially, the thin oxide characteristic seems to be affected largely by wafer cleaning and oxidation in air. On the basis of these, tunnel type EEPROM cell is fabricated by 3um CMOS process and its characteristic is studied. Tunnel oxide thickness(100\ulcorner is chosen to allow Fowler-Nordheim tunneling to charge the floating gate at the desired programming voltage and tunnel area(2x2um\ulcorneris chosen to increase capacitive coupling ratio. For program operation, high voltage (20-22V) is applied to the control gate, while both drain and source are gdrounded. The drain voltage for erase is 16V. It is shown that charge retention characteristics is not limited by leakage in the oxide and program/erase endurance is over 10E4 cycles of program erase operation.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.294-300
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• 2002

In this study, we fabricated thermopile infrared sensor with floating membrane structure. Floating membrane was formed by SOI(Silicon On Insulator) structure. In SOI structure, silicon dioxide layer between top silicon layer and bottom silicon substrate was etched by HF solution, then membrane was floated over substrate. After membrane was floated, thermopile pattern was formed on membrane. By insertion of SOI technology, we could obtain thermal isolation structure easily and passivation process for sensor pattern protection was not required during fabrication process. Then, the amplifier circuit for thermopile sensor was fabricated by using $1.5{\mu}m$ CMOS process. The voltage gain of fabricated amplifier was about two hundred.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.