• 제목/요약/키워드: CMOS fabrication process

검색결과 113건 처리시간 0.023초

CMOS 표준 공정을 통한 SPM 프로브의 제작 및 그 성능 평가 (Fabrication of the FET-based SPM probe by CMOS standard process and its performance evaluation)

  • 이훈택;김준수;신금재;문원규
    • 센서학회지
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    • 제30권4호
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    • pp.236-242
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    • 2021
  • In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

CMOS공정 기반의 저전력 NO 마이크로가스센서의 제작 (Fabrication of low power NO micro gas senor by using CMOS compatible process)

  • 신한재;송갑득;이홍진;홍영호;이덕동
    • 센서학회지
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    • 제17권1호
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    • pp.35-40
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    • 2008
  • Low power bridge type micro gas sensors were fabricated by micro machining technology with TMAH (Tetra Methyl Ammonium Hydroxide) solution. The sensing devices with different heater materials such as metal and poly-silicon were obtained using CMOS (Complementary Metal Oxide Semiconductor) compatible process. The tellurium films as a sensing layer were deposited on the micro machined substrate using shadow silicon mask. The low power micro gas sensors showed high sensitivity to NO with high speed. The pure tellurium film used micro gas sensor showed good sensitivity than transition metal (Pt, Ti) used tellurium film.

Process Parameter의 Modelling에 의한 BiCMOS 소자 설계의 최적화 방안에 관한 연구 (A Study on the Computer Modelling with Process Parameters for the Optimization of BiCMOS Device)

  • 강이구;김태익;우영신;이계훈;성만영;이철진
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1994년도 하계학술대회 논문집 C
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    • pp.1460-1462
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    • 1994
  • BiCMOS is the newly developed technology that integrates both CMOS and bipolar structures on the same integrated circuit. Improved performance can be obtained from combining the advantages of high density and low power in CMOS with the speed and current capibility advantages by bipolar. However, the major drawbacks to BiCMOS are high cost, long fabrication time and difficulty of merging CMOS with bipolar without degrading of device Performance because CMOS and bipolar share same process step. In this paper, N-Well CMOS oriented BiCMOS process and optimization of device performance are studied when N-Well links CMOS with bipolar process step by 2D process and 3D Device simulation. From the simulation, Constriction of linking process step has been understood and provided to give the method of choosing BiCMOS for various analog design request.

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제조 공정상 랜덤 특성을 고려한 IC 최악조건 해석 (IC Worst Case Analysis Considered Random Fluctuations on Fabrication Process)

  • 박상봉;박노경;전흥우;문대철;차균현
    • 대한전자공학회논문지
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    • 제25권6호
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    • pp.637-646
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    • 1988
  • The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

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The Active Dissolved Wafer Process (ADWP) for Integrating single Crystal Si MEMS with CMOS Circuits

  • Karl J. Ma;Yogesh B. Glanchandani;Khalil Najafi
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권4호
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    • pp.273-279
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    • 2002
  • This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

CMOS 공정을 이용한 마이크로 센서의 설계 및 제작 (Design and Fabrication of Micro-sensors Using CMOS Technology)

  • 이성필;이지공;장중원;김주남;이용재;양흥열
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2007년도 추계학술대회 논문집
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    • pp.347-348
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    • 2007
  • On-chip micro humidity sensor, using $CN_x$ films for the sensing material, was designed, simulated, and fabricated with Op amp based readout circuit and diode temperature sensors. To compensate the temperature and other gases, two methods were applied. One is wheatstone-bridge with reference FET that eliminates other undesirable chemical species, and the other is a diode temperature sensor to compensate the temperature effect. $CN_x$ film can be a new humidity sensing material, and has a strong potential to adapt to smart sensors or multi-sensors using MEMS or nano-technology. A particular design technology for integration of sensors and systems together was proposed that whole fabrication process could be achieved by a standard CMOS process.

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CMOS 공정에 적합한 AlN 압전 마이크로 발전기의 제작 및 특성 (Fabrication of AlN piezoelectric micro power generator suitable with CMOS process and its characteristics)

  • 정귀상;이병철
    • 센서학회지
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    • 제19권3호
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    • pp.209-213
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    • 2010
  • This paper describes the fabrication and characteristics of AlN piezoelectric MPG(micro power generator). The micro energy harvester was fabricated to convert ambient vibration energy to electrical power as a AlN piezoelectric cantilever with Si proof-mass. To be compatible with CMOS process, AlN thin film was grown at low temperature by RF magnetron sputtering and micro power generators were fabricated by MEMS technologies. X-ray diffraction pattern proved that the grown AlN film had highly(002) orientation with low value of FWHM(full width at the half maximum, $\theta=0.276^{\circ}$) in the rocking curve around(002) reflections. The implemented harvester showed the $198.5\;{\mu}m$ highest membrane displacement and generated 6.4 nW of electrical power to $80\;k{\Omega}$ resistive load with $22.6\;mV_{rms}$ voltage from 1.0 G acceleration at its resonant frequency of 389 Hz. From these results, the AlN piezoelectric MPG will be possible to suitable with the batch process and confirm the possibility for power supply in portable, mobile and wearable microsystems.

CMOS 공정을 이용한 온도 센서 회로의 설계 (A Design of Temperature Sensor Circuit Using CMOS Process)

  • 최진호
    • 한국정보통신학회논문지
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    • 제13권6호
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    • pp.1117-1122
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    • 2009
  • 본 논문에서는 온도 센서 및 온도 측정을 위한 제어회로를 설계하였다. 설계된 회로는 기존의 방법들과는 달리 일반적인 CMOS(Complementary Metal Oxide Semiconductor) 공정에서 추가 공정없이 제작 가능하도록 설계하였으며, 온도는 디지털 값으로 출력 되도록 구성하였다. 설계되어진 회로는 5volts 공급전압을 사용하였으며, 0.5${\mu}m$ CMOS 공정을 사용하였다. 온도 측정을 위한 회로는 PWM(Pulse Width Modulation) 제어회로, VCO(Voltage controlled oscillator), 카운터 그리고 레지스터로 구성되어 있다. PWM 제어회로의 동작 주파수는 23kHz 이며, VCO의 동작 주파수는 416kHz, 1MHz, 2MHz를 사용하였다. 회로의 동작은 SPICE(Simulation Program with Integrated Circuit Emphasis)를 사용하여 확인 하였다.

Printed CMOS 공정기술을 이용한 MASK ROM 설계 (MASK ROM IP Design Using Printed CMOS Process Technology)

  • 장지혜;하판봉;김영희
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2010년도 춘계학술대회
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    • pp.788-791
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    • 2010
  • 본 논문에서는 인쇄공정기술로써 ETRI $0.8{\mu}m$ CMOS 공정을 사용하여 수동형 인쇄 RFID 태그칩용 64bit ROM을 설계하였다. 먼저 태그 칩의 제작단가를 줄이기 위하여 기존 실리콘 기반의 복잡한 리소그래피 공정을 사용하지 않고 게이트 단자인 폴리 층을 프린팅 기법 중 하나인 임프린트 공정을 사용하여 구현하였다. 그리고 �弼壅� ROM 셀 회로는 기존 ROM 셀 회로의 NMOS 트랜지스터대신에 CMOS 트랜스미션 게이트를 사용함으로써 별도의 BL 프리차지 회로와 BL 감지 증폭기가 필요 없이 출력 버퍼만으로 데이터를 읽어낼 수 있도록 하였다. $0.8{\mu}m$ CMOS 공정을 이용하여 설계된 8 행 ${\times}$ 8 열의 어레이를 갖는 64b ROM의 동작전류는 $9.86{\mu}A$이며 레이아웃 면적은 $311.66{\times}490.59{\mu}m^2$이다.

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A 10-bit Current-steering DAC in 0.35-μm CMOS Process

  • Cui, Zhi-Yuan;Piao, Hua-Lan;Kim, Nam-Soo
    • Transactions on Electrical and Electronic Materials
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    • 제10권2호
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    • pp.44-48
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    • 2009
  • A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.