• Journal of Sensor Science and Technology
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• v.30 no.4
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• pp.236-242
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• 2021

In this paper, we report the fabrication of the tip-on-gate of a field-effect-transistor (ToGoFET) probe using a standard complementary metal-oxide-semiconductor (CMOS) process and the performance evaluation of the fabricated probe. After the CMOS process, I-V characteristic measurement was performed on the reference MOSFET. We confirmed that the ToGoFET probe could be operated at a gate voltage of 0 V due to channel ion implantation. The transconductance at the operating point (Vg = 0 V, Vd = 2 V) was 360 ㎂/V. After the fabrication process was completed, calibration was performed using a pure metal sample. For sensitivity calibration, the relationship between the input voltage of the sample and the output current of the probe was determined and the result was consistent with the measurement result of the reference MOSFET. An oxide sample measurement was performed as an example of an application of the new ToGoFET probe. According to the measurement, the ToGoFET probe could spatially resolve a hundred nanometers with a height of a few nanometers in both the topographic image and the ToGoFET image.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.35-40
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• 2008

Low power bridge type micro gas sensors were fabricated by micro machining technology with TMAH (Tetra Methyl Ammonium Hydroxide) solution. The sensing devices with different heater materials such as metal and poly-silicon were obtained using CMOS (Complementary Metal Oxide Semiconductor) compatible process. The tellurium films as a sensing layer were deposited on the micro machined substrate using shadow silicon mask. The low power micro gas sensors showed high sensitivity to NO with high speed. The pure tellurium film used micro gas sensor showed good sensitivity than transition metal (Pt, Ti) used tellurium film.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1460-1462
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• 1994

BiCMOS is the newly developed technology that integrates both CMOS and bipolar structures on the same integrated circuit. Improved performance can be obtained from combining the advantages of high density and low power in CMOS with the speed and current capibility advantages by bipolar. However, the major drawbacks to BiCMOS are high cost, long fabrication time and difficulty of merging CMOS with bipolar without degrading of device Performance because CMOS and bipolar share same process step. In this paper, N-Well CMOS oriented BiCMOS process and optimization of device performance are studied when N-Well links CMOS with bipolar process step by 2D process and 3D Device simulation. From the simulation, Constriction of linking process step has been understood and provided to give the method of choosing BiCMOS for various analog design request.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.637-646
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• 1988

The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.4
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• pp.273-279
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• 2002

This paper presents a fabrication technology for the integration of single crystal Si microstructures with on-chip circuitry. It is a dissolved wafer technique that combines an electro-chemical etch-stop for the protection of circuitry with an impurity-based etch-stop for the microstructures, both of which are defined in an n-epi layer on a p-type Si wafer. A CMOS op. amp. has been integrated with $p^{++}$ Si accelerometers using this process. It has a gain of 68 dB and an output swing within 0.2 V of its power supplies, unaffected by the wafer dissolution. The accelerometers have $3{\;}\mu\textrm{m}$ thick suspension beams and $15{\;}\mu\textrm{m}$ thick proof masses. The structural and electrical integrity of the fabricated devices demonstrates the success of the fabrication process. A variety of lead transfer methods are shown, and process details are discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.347-348
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• 2007

On-chip micro humidity sensor, using $CN_x$ films for the sensing material, was designed, simulated, and fabricated with Op amp based readout circuit and diode temperature sensors. To compensate the temperature and other gases, two methods were applied. One is wheatstone-bridge with reference FET that eliminates other undesirable chemical species, and the other is a diode temperature sensor to compensate the temperature effect. $CN_x$ film can be a new humidity sensing material, and has a strong potential to adapt to smart sensors or multi-sensors using MEMS or nano-technology. A particular design technology for integration of sensors and systems together was proposed that whole fabrication process could be achieved by a standard CMOS process.

• Journal of Sensor Science and Technology
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• v.19 no.3
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• pp.209-213
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• 2010

This paper describes the fabrication and characteristics of AlN piezoelectric MPG(micro power generator). The micro energy harvester was fabricated to convert ambient vibration energy to electrical power as a AlN piezoelectric cantilever with Si proof-mass. To be compatible with CMOS process, AlN thin film was grown at low temperature by RF magnetron sputtering and micro power generators were fabricated by MEMS technologies. X-ray diffraction pattern proved that the grown AlN film had highly(002) orientation with low value of FWHM(full width at the half maximum, $\theta=0.276^{\circ}$) in the rocking curve around(002) reflections. The implemented harvester showed the $198.5\;{\mu}m$ highest membrane displacement and generated 6.4 nW of electrical power to $80\;k{\Omega}$ resistive load with $22.6\;mV_{rms}$ voltage from 1.0 G acceleration at its resonant frequency of 389 Hz. From these results, the AlN piezoelectric MPG will be possible to suitable with the batch process and confirm the possibility for power supply in portable, mobile and wearable microsystems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1117-1122
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• 2009

In this work, temperature sensor and control circuit for measuring temperature are proposed. The proposed circuit can be fabricated without additional CMOS fabrication process and the output of proposed circuit is digital value. The supply voltage is 5volts and the circuit is designed by using 0.5${\mu}m$ CMOS process. The circuit for measuring temperature consists of PWM control circuit, VCO, counter and register. consisted The frequency of PWM control circuit is 23kHz and the frequency of VCO is 416kHz, 1MHz and 2MHz, respectively. The circuit operation is analyzed by using SPICE.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.788-791
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• 2010

We design 64-bit ROM IP for RFID tag chips using printed CMOS non-volatile memory IP design technology for a printed CMOS process. The proposed 64-bit ROM circuit is using ETRI's $0.8{\mu}m$ CMOS porocess, and is expected to reduce process complexity and cost of RFID tag chips compared to that using a conventional silicon fabrication based on a complex lithography process because the poly layer in a gate terminal is using printing technology of imprint process. And a BL precharge circuit and a BL sense amplifier is not required for the designed cell circuit since it is composed of a transmission gate instead of an NMOS transistor of the conventional ROM circuit. Therefore an output datum is only driven by a DOUT buffer circuit. The Operation current and layout area of the designed ROM of 64 bits with an array of 8 rows and 8 columns using $0.8{\mu}m$ ROM process is $9.86{\mu}A$ and $379.6{\times}418.7{\mu}m^2$.

• Transactions on Electrical and Electronic Materials
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• v.10 no.2
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.