• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.564-568
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• 2014

We present a 25-Gb/s optical transmitter composed of a Si ring modulator and CMOS driver circuit. The Si ring modulator is realized with 220-nm Si-on-insulator process and the driver circuit with 65-nm CMOS process. The modulator and the driver are hybrid-integrated on the printed circuit board with bonding wires. The driver is designed so that the parasitic bonding wire inductance provides enhanced driver bandwidth. The transmitter successfully demonstrates 25-Gb/s operation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.1
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• pp.88-95
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• 2013

We propose a novel driver circuit design using $0.18{\mu}m$ CMOS process technology that drives a 1550 nm high-speed VCSEL used in optical transceiver. We report a distinct improvement in bandwidth, voltage gain and eye diagram at 3.1Gb/s data rate in comparison with existing topology. In this paper, the design and layout of a 3.1Gb/s VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.5
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.1
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• pp.87-96
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• 2019

Flexible organic light-emitting diode (OLED) displays with organic thin-film transistors (OTFTs) backplanes have been studied. A gate driver is required to drive the OLED display. The gate driver is integrated into the panel to reduce the manufacturing cost of the display panel and to simplify the module structure using fabrication methods based on low-temperature, low-cost, and large-area printing processes. In this paper, pseudo complementary metal oxide semiconductor (CMOS) logic gates are implemented using OTFTs for the gate driver integrated in the flexible OLED display. The pseudo CMOS inverter and NAND gates are designed and fabricated on a flexible plastic substrate using inkjet-printed OTFTs and the same process as the display. Moreover, the operation of the logic gates is confirmed by measurement. The measurement results show that the pseudo CMOS inverter can operate at input signal frequencies up to 1 kHz, indicating the possibility of the gate driver being integrated in the flexible OLED display.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.621-622
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• 2006

This paper presents the design of LVDS(Low-Voltage-Differential-Signaling) driver circuit for Gb/s-per-pin operation using BiCMOS process technology. To reduce chip area, LVDS driver's switching devices were replaced with lateral bipolar devices. The designed lateral bipolar transister's common emitter current gain($\beta$) is 20 and device's emitter size is 2*10um. Also the proposed LVDS driver is operated at 2.5V and the maximum data rate is 2.8Gb/s approximately.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.561-567
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• 2017

This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.50-57
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• 2008

In this paper, a high-efficiency charge pump for use in CMOS image sensor(CIS) is proposed. The proposed charge pump pursues high pumping efficiency by minimizing the switching and reversion losses by taking advantage of operation characteristics of CIS. That is, the proposed charge pump minimizes the switching loss by dynamically controlling the size of clock driver, pumping capacitor, and charge transfer switch based on the operation phase of CIS pixel sensor. The charge pump also minimizes the reversion loss by guaranteeing a sufficient non-overlapping period of local clocks using a tri-state local clock driver adapting the schmitt trigger. Comparison results using a 0.13-um CMOS process technology indicate that the proposed charge pump achieves up to 49.1% reduction on power consumption under no loading current condition as compared to conventional charge pump. They also indicate that the charge pump provides 19.0% reduction on power consumption under the maximum loading current condition.

• Journal of Information Display
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• v.3 no.3
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• pp.35-43
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• 2002

Silicon-based 0.69-inch AMOEL microdisplay with integrated driver and timing controller circuits for microdisplay applications has been developed using 0.35 ${\mu}m$ l-poly 4-metal standard CMOS process with 5 V CMOS devices and CMP (Chemical Mechanical Polishing) technology. To reduce the large data programming time consumed in a conventional current programming pixel circuit technique and to achieve uniform display, de-amplifying current mirror pixel circuit and the current-mode data driver circuit with threshold roltage compensation are proposed. The proposed current-mode data driver circuit is inherently immune to the ground-bouncing effect. The Monte-Carlo simulation results show that the proposed current-mode data driver circuit has channel-to-channel non-uniformity of less than ${\pm}$0.6 LSB under ${\pm}$70 mV threshold voltage variaions for both NMOS and PMOS transistors, which gives very good display uniformity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.6
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• pp.427-434
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• 2013

In this paper, the design and layout of a 2.5 Gbps arrayed VCSEL driver for optical transceiver having arrayed multi-channel of integrating module is confirmed. In this paper, a 4 channel 2.5 Gbps VCSEL (vertical cavity surface emitting laser) driver array with automatic optical power control is implemented using $0.18{\mu}m$ CMOS process technology that drives a $1550{\mu}m$ high speed VCSEL used in optical transceiver. To enhance the bandwidth of the optical transmitter, active feedback amplifier with negative capacitance compensation is exploited. We report a distinct improvement in bandwidth, voltage gain and operation stability at 2.5Gbps data rate in comparison with existing topology. The 4-CH chip consumes only 140 mW of DC power at a single 1.8V supply under the maximum modulation and bias currents, and occupies the die area of $850{\mu}m{\times}1,690{\mu}m$ excluding bonding pads.