• Imaging Science in Dentistry
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• v.52 no.1
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• pp.93-101
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• 2022

Purpose: This study compared the effectiveness of complementary metal-oxide semiconductors (CMOS) and photostimulable phosphor (PSP) plates as intraoral imaging systems in terms of time efficacy, patient comfort, and subjective image quality assessment in real clinical settings. Materials and Methods: Fifty-eight patients (25 women and 33 men) were included. Patients were referred for a full-mouth radiological examination including 1 bitewing radiograph (left and right) and 8 periapical radiographs for each side (left maxilla/mandible and right maxilla/mandible). For each patient, 1 side of the dental arch was radiographed using a CMOS detector, whereas the other side was radiographed using a PSP detector, ensuring an equal number of left and right arches imaged by each detector. Clinical application time, comfort/pain, and subjective image quality were assessed for each detector. Continuous variables were summarized as mean±standard deviation. Differences between detectors were evaluated using repeated-measures analysis of variance. P<0.05 was accepted as significant. Results: The mean total time required for all imaging procedures with the CMOS detector was significantly lower than the mean total time required for imaging procedures with PSP (P<0.05). The overall mean patient comfort scores for the CMOS and PSP detectors were 4.57 and 4.48, respectively, without a statistically significant difference (P>0.05). The performance of both observers in subjectively assessing structures was significantly higher when using CMOS images than when using PSP images for all regions (P<0.05). Conclusion: The CMOS detector was found to be superior to the PSP detector in terms of clinical time efficacy and subjective image quality.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.1045-1050
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• 2008

In this paper presents a CMOS RF receiver for IR-UWB wireless communications is presented. The impulse radio based UWB receiver adopts the non-coherent demodulation that simplifies the receiver architecture and reduces power consumption. The IR-UWB receiver consists of LNA, envelop detector, VGA, and comparator and the receiver including envelope detector, VGA, and comparator is fabricated on a single chip using $0.18{\mu}m$ CMOS technology. The measured sensitivity of IR-UWB receiver is down to -70 dBm and the BER $10^{-3}$, respectively at data rate 1 Mbps. The current consumption of IR-UWB receiver except external LNA is 5 mA at 1.8 V.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.583-590
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• 2002

In this paper, a new Silicon on Insulator (SOI)-based photodetector was proposed, and its basic operation principle was explained. Fabrication steps of the detector are compatible with those of conventional SOI CMOS technology. With the proposed structure, RGB (Read, Green, Blue) which are three primary colors of light can be realized without using any organic color filters. It was shown that the characteristics of the SOI-based detector are better than those of bulk-based detector. To see the response characteristics to the green (G) among RGB, SOI and bulk NMOSFETS were fabricated using $1.5\mu m$ CMOS technology and characterized. We obtained optimum optical response characteristics at $V_{GS}=0.35 V$ in NMOSFET with threshold voltage of 0.72 V. Drain bias should be less than about 1.5 V to avoid any problem from floating body effect, since the body of the SOI NMOSFET was floated. The SOI and the bulk NMOSFETS shown maximum drain currents at the wavelengths of incident light around 550 nm and 750 nm, respectively. Therefore the SOI detector is more suitable for the G color detector.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.385-388
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• 2003

In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1027-1033
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• 2013

In this work, a D-band imaging detector has been developed in a 65-nm CMOS technology for high frequency imaging application. The circuit was designed based on the resistive self-mixing of MOSFET devices. The fabricated detector exhibits a maximum responsivity of 400 V/W and minimum NEP of 100 $pW/Hz^{1/2}$ at 145 GHz. The chip size is $400{\mu}m{\times}450{\mu}m$ including the probing pads and a balun, while the core of the circuit occupies only $150{\mu}m{\times}100{\mu}m$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.72-73
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• 2005

In this paper, the simulation of the n-p-n-p layer stacked color detector is presented. A color detector based on vertically integrated structures of silicon can overcome color moire or color aliasing effect. The color detector is designed to separate the fundamental chromatic components at each junction and exhibits maxima of the spectral sensitivity at red, green, and blue region, respectively. From this result, it is observed that the spectral response can be controlled by the doping concentration and structure of the devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.7
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• pp.791-794
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• 2014

In this work, a 300 GHz imaging detector has been developed and image has been acquired in a 65-nm CMOS technology. The circuit was designed based on the square-law of MOSFET devices. The fabricated detector exhibits a maximum responsivity of 2,270 V/W and minimum NEP of $38pW/Hz^{1/2}$ at 285 GHz, and NEP< ${\sim}200pW/Hz^{1/2}$ for 250~305 GHz range. The chip size is $400{\mu}m{\times}450{\mu}m$ including the probing pads and a balun, while the core of the circuit occupies only $150{\mu}m{\times}100{\mu}m$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.50-57
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• 2007

A 5Gbps CMOS　adaptive feed-forward equalizer designed for backplane applications is described. The equalizer has adaptive feedback circuits to control the compensating gain of the equalizing filter, which uses a phase detector in clock recovery circuit to detect ISI (Inter-Symbol Interference) level. This makes the equalizer operate adaptively for a various channel length of backplane environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.10C
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• pp.987-992
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• 2002

In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.

• Journal of the Optical Society of Korea
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• v.16 no.1
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• pp.1-5
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• 2012

This paper describes a 150-Mb/s monolithic optical receiver for plastic optical fiber link using a standard CMOS technology. The receiver integrates a photodiode using an N-well/P-substrate junction, a pre amplifier, a post amplifier, and an output driver. The size, PN-junction type, and the number of metal fingers of the photodiode are optimized to meet the link requirements. The N-well/P-substrate photodiode has a 200-${\mu}m$ by 200-${\mu}m$ optical window, 0.1-A/W responsivity, 7.6-pF junction capacitance and 113-MHz bandwidth. The monolithic receiver can successfully convert 150-Mb/s optical signal into digital data through up to 30-m plastic optical fiber link with -10.4 dBm of optical sensitivity. The receiver occupies 0.56-$mm^2$ area including electrostatic discharge protection diodes and bonding pads. To reduce unnecessary power consumption when the light is not over threshold or not modulating, a simple light detector and a signal detector are introduced. In active mode, the receiver core consumes 5.8-mA DC currents at 150-Mb/s data rate from a single 3.3 V supply, while consumes only $120{\mu}W$ in the sleep mode.