• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.185-189
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• 2017

This paper proposes a low power frequency divider for an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) was designed, along with a current-mode logic (CML) frequency divider in order to obtain a broadband and high-frequency operation. A ring oscillator was designed to operate at 1.2 GHz, and the ILFD was used to divide the frequency of its input signal by two. The structure of the ILFD is similar to that of the ring oscillator in order to ensure the frequency alignment between the oscillator and the ILFD. The CML frequency divider was used as the second stage of the divider. The proposed frequency divider was applied in a conventional PLL design, using a 0.18 ${\mu}m$ CMOS process. Simulation shows that the proposed divide-by-two ILFD and the divide-by-eight CML frequency dividers operated as expected for an input frequency of 1.2 GHz, with a power consumption of 30 mW.

• Transactions on Electrical and Electronic Materials
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• v.11 no.1
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• pp.24-28
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• 2010

A simulation study of a current-mode direct current (DC)-DC buck converter is presented in this paper. The converter, with a fully integrated power module, is implemented by using sense method metal-oxide-semiconductor field-effect transistor (MOSFET) and bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. When the MOSFET is used in a current sensor, the sensed inductor current with an internal ramp signal can be used for feedback control. In addition, the BiCMOS technology is applied in the converter for an accurate current sensing and a low power consumption. The DC-DC converter is designed using the standard $0.35\;{\mu}m$ CMOS process. An off-chip LC filter is designed with an inductance of 1 mH and a capacitance of 12.5 nF. The simulation results show that the error between the sensing signal and the inductor current can be controlled to be within 3%. The characteristics of the error amplification and output ripple are much improved, as compared to converters using conventional CMOS circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.678-681
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• 2009

A single-pixel photon counter is designed using a folded cascode CMOS operational amplifier which is self-biased. Since there is no need for a voltage bias circuit, the layout area and power consumption of the designed counter are reduced. The signal voltage of the designed charge sensitive amplifier (CSA) with the MagnaChip $0.18{\mu}m$ CMOS process is simulated to be 138mv, near the theoretical voltage of 151mV. And the layout area of the designed counter is $100{\mu}m{\times}100{\mu}m$.

• Journal of IKEEE
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• v.25 no.1
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• pp.133-138
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• 2021

We propose a Ku-band three-stack CMOS power amplifier to enhance the output power and efficiency. To minimize the dc power consumption, the driver stage is designed using common-source structure. To obtain high output power and utilize a voltage combining method, the power stage is designed using stack structure. To verify the proposed power amplifier structure, we design a Ku-band power amplifier using 65-nm RFCMOS process which provide nine metal layers. The P1dB, power-added efficiency, and gain are higher than 20 dBm, 23 dB, and 25%, respectively, while the operating frequency is 14 GHz-16 GHz.

• Journal of Advanced Information Technology and Convergence
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• v.10 no.1
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• pp.37-43
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• 2020

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (C_ex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.26-33
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• 2010

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.225-228
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• 2012

In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.50-59
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• 2016

This work shows that the design and test results of a power amplifier(PA) with broadband and high linearity for 4G applications in $0.11{\mu}m$ CMOS process. A 1:2-transformer is designed for load impedance matching of PA and a inter-stage matching is implemented for a linearity. A designed PA achieves more than 27.3 dBm of linear output power and 26.1 % of power-added efficiency(PAE) under an adjacent channel leakage ratio(ACLR) of -30 dBc for a LTE 16-QAM 10 MHz signal with a carrier frequency range of 1.8 to 2.3 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.73-78
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• 2011

A frequency synthesizer for DAB applications is designed using $0.18{\mu}m$ CMOS process with 1.8V supply. NP-core type is chosen for VCO core to improve low power characteristic and symmetric characteristic of output waveform. VCO range is 1302.34 MHz - 1949.51 MHz using switchable capacitor bank and varactor bank. Varactor biases that improve varactor capacitance characteristics were minimized as two, $K_{vco}$(VCO gain) is maintained using technique of varactor bank switching. Intervals of $K_{vco}$ are maintained adding VCO frequency compensation logic. Each block of VCO and frequency synthesizer designed $0.18{\mu}m$ CMOS process with 1.8V supply is verified by Cadence Spectre, measured VCO consumes 9mA current, and is 39.8% tuning range, total power consumption of the frequency synthesizer is 18mW.

• Journal of IKEEE
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• v.23 no.2
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• pp.681-686
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• 2019

This paper proposes a CMOS temperature sensor using inverter delay chains of the same size based on the pulse shrinking method. A temperature-pulse converter (TPC) uses two different temperature delay lines with inverter chains to generate a pulse in proportion to temperature, and a time-digital converter (TDC) shrinks the pulse using inverter chains of the same size to convert pulse width into a digital value to be insensitive to process changes. The chip was implemented with a $0.49{\mu}m{\times}0.23{\mu}m$ area using a $0.35{\mu}m$ CMOS process with a supply voltage of 3.3V. The measurement results show a resolution of $0.24^{\circ}C/bit$ for 9-bit data for a temperature sensor range of $0^{\circ}C$ to $100^{\circ}C$.