• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.593-594
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• 2008

In this article, process voltage temperature (PVT) compensated on-chip oscillator is implemented by using proportional to absolute temperature (PTAT) circuit and process compensator. Process compensator circuit based on current subtracter and PTAT circuit are proposed for compensation of oscillation frequency to cope with process variation and temperature variation. All circuit can operate in the range of $3.5{\sim}5\;V$ supply voltage. It can be applied to PVT insensitive low frequency clock reference generator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.131-136
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• 2008

Two Ka-band 3-stage power amplifiers were designed and fabricated using $0.18-{\mu}m$ CMOS technology. For low loss matching networks for the amplifiers, two substrate-shielded transmission line structures, having good modeling accuracy up to 40 GHz were used. The measured insertion loss of substrate-shielded microstrip-line (MSL) was 0.5 dB/mm at 27 GHz. A 3-stage CMOS amplifier using substrate-shielded MSL achieved a 14.7-dB small-signal gain and a 14.5-dBm output power at 27 GHz in a compact chip area of 0.83$mm^2$. The measured insertion loss of substrate-shielded coplanar waveguide (CPW) was 1.0 dB/mm at 27 GHz. A 3-stage amplifier using substrate-shielded CPW achieved a 12-dB small-signal gai and a 12.5-dBm output power at 26.5 GHz. This results shows a potential of CMOS technology for low cost short-range wireless communication components and system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.117-122
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• 2016

In this paper, we propose 24-GHz CMOS radio frequency (RF) power amplifier for short-range automotive collision avoidance radars. This circuit contains common source stage with inter-stages conjugate matching circuit as a class-A mode amplifier. The proposed circuit is designed using TSMC $0.13-{\mu}m$ mixed signal/RF CMOS process ($f_T/f_{MAX}=120/140GHz$). It operates at the supply voltage of 2V, and it is designed to have high power gain, low insertion loss and low noise figure in the low supply voltage. To reduce total chip area, the circuit used transmission lines instead of the bulky real inductor. The designed CMOS power amplifier showed the smallest chip size of $0.1mm^2$, the lowest power consumption of 40mW, the highest power gain of 26.5dB, the highest saturated output power of 19.2dBm and the highest maximum power-added efficiency of 17.2% as compared to recently reported results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.6-11
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• 2007

This paper proposes CMOS optical receivers to reduce effective area and pulse width distortion (PWD) in high definition digital audio interfaces. To mitigate effective area and PWD, proposed receivers include a frans-impedance amplifier (TIA) with dual output and a level shifter with threshold convergence, respectively. Proposed circuits are fabricated using $0.25{\mu}m$ CMOS process and measured result demonstrated the effective area of $270\times120{\mu}m^2$ and PWD of ${\pm}3%$ for the receiver with a dual output TIA, and the effective area of $410\times140{\mu}m^2$ and PWD of ${\pm}2%$ for the receiver with a threshold convergence level shifter.

• Journal of IKEEE
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• v.18 no.1
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• pp.119-127
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• 2014

This paper presents a CMOS readout circuit for MEMS(Micro Electro Mechanical System) acceleration sensors. It consists of a MEMS accelerometer, a capacitance to voltage converter(CVC) and a second-order switched-capacitor ${\Sigma}{\Delta}$ modulator. Correlated-double-sampling(CDS) and chopper-stabilization(CHS) techniques are used in the CVC and ${\Sigma}{\Delta}$ modulator to reduce the low-frequency noise and DC offset. The sensitivity of the designed CVC is 150mV/g and its non-linearity is 0.15%. The duty cycle of the designed ${\Sigma}{\Delta}$ modulator output increases about 10% when the input voltage amplitude increases by 100mV, and the modulator's non-linearity is 0.45%. The total sensitivity is 150mV/g and the power consumption is 5.6mW. The proposed circuit is designed in a 0.35um CMOS process with a supply voltage of 3.3V and a operating frequency of 2MHz. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.895-902
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• 2014

This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a $0.18-{\mu}m$ CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of -30 dBc.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.158-165
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• 2013

In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in $0.18-{\mu}m$ CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.1
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• pp.94-101
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• 2009

This paper presents scalable modeling of spiral inductors for RFIC design based on $0.13{\mu}m$ RF CMOS process. For scalable modeling, several inductor patterns are designed and fabricated with variations of width, number of turns and inner radius. Feeding structures are optimized for accurate de-embedding of pad effects. After measuring the S parameters of the fabricated patterns, double-$\pi$ equivalent circuit parameters are extracted for each device and their geometrical dependences are modeled as scalable functions. The inductor library provides two types of models including standard and symmetric inductors. Standard and symmetric inductors have the range of $0.12{\sim}10.7nH$ and $0.08{\sim}13.6nH$ respectively. The models are valid up to 30GHz or self-resonance frequency. Through this research, a scalable inductor library with an error rate below 10% is developed for $0.13{\mu}m$ RF CMOS process.