• Korean Journal of Materials Research
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• v.23 no.6
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• pp.299-303
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• 2013

In this study, a micro gas sensor for $NO_x$ was fabricated using a microelectromechanical system (MEMS) technology and sol-gel process. The membrane and micro heater of the sensor platform were fabricated by a standard MEMS and CMOS technology with minor changes. The sensing electrode and micro heater were designed to have a co-planar structure with a Pt thin film layer. The size of the gas sensor device was about $2mm{\times}2mm$. Indium oxide as a sensing material for the $NO_x$ gas was synthesized by a sol-gel process. The particle size of synthesized $In_2O_3$ was identified as about 50 nm by field emission scanning electron microscopy (FE-SEM). The maximum gas sensitivity of indium oxide, as measured in terms of the relative resistance ($R_s=R_{gas}/R_{air}$), occurred at $300^{\circ}C$ with a value of 8.0 at 1 ppm $NO_2$ gas. The response and recovery times were within 60 seconds and 2 min, respectively. The sensing properties of the $NO_2$ gas showed good linear behavior with an increase of gas concentration. This study confirms that a MEMS-based gas sensor is a potential candidate as an automobile gas sensor with many advantages: small dimension, high sensitivity, short response time and low power consumption.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.11
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• pp.914-920
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• 2000

When the charge-trap type SONOS(polysilicon-oxide-nitride-oxide-semiconductor) cells are used to flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM(Nonvolatile Semiconductor Memory) cells were fabricated using 0.35 ㎛ standard memory cell embedded logic process including the ONO cell process, based on retrograde twin-well, single-poly, single metal CMOS(Complementary Metal Oxide Semiconductor) process. The thickness of ONO triple-dielectric for the memory cell is tunnel oxide of 24 $\AA$, nitride of 74 $\AA$, blocking oxide of 25 $\AA$, respectively. The program mode(V$\_$g/=7, 8, 9 V, V$\_$s/=V$\_$d/=-3 V, V$\_$b/=floating) and the erase mode(V$\_$g/=-4, -5, -6 V, V$\_$s/=V$\_$d/=floating, V$\_$b/=3 V) by MFN(Modified Fowler-Nordheim) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation(ΔV$\_$th/, S, G$\_$m/) characteristics than channel MFN tunneling operation. Also, the program inhibit conditins of unselected cell for separated source lines NOR-type flash memory application were investigated. we demonstrated that the phenomenon of the program disturb did not occur at source/drain voltage of 1 V∼12 V and gate voltage of -8 V∼4 V.

• Journal of IKEEE
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• v.22 no.2
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• pp.408-412
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• 2018

In this paper, a 26GHz variable gain amplifier fabricated using a 40nm CMOS process is studied. In the case of an automobile radar using 79 GHz, it is advantageous in designing and driving to drive down to a low frequency band or to use a low frequency band before up conversion rather than designing and matching the entire circuit to 79 GHz in terms of frequency characteristics. In the case of a Phased Array System that uses time delay through TTD (True Time Delay) in practice, down conversion to a lower frequency is advantageous in realizing a real time delay and reducing errors. For a VGA (Variable Gain Amplifier) operating in the 26GHz frequency band that is 1/3 of the frequency of 79GHz, VDD : 1V, Bias 0.95V, S11 is designed to be <-9.8dB (Mea. High gain mode) and S22 < (Mea. high gain mode), Gain: 2.69dB (Mea. high gain mode), and P1dB: -15 dBm (Mea. high gain mode). In low gain mode, S11 is <-3.3dB (Mea. Low gain mode), S22 <-8.6dB (Mea. low gain mode), Gain: 0dB (Mea. low gain mode), P1dB: -21dBm (Mea. Low gain mode).

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.181-191
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• 2000

In this paper, two schemes of generating reference voltages using enhancement-mode MOS transistors and resistors are proposed. The first one is a voltage-mode scheme where the temperature compensation is made by summing a voltage component proportional to a threshold voltage and a voltage component proportional to a thermal voltage. In the second one, that is a current-mode scheme, the temperature compensation is made by summing a current component proportional to a threshold voltage and a current component proportional to a thermal voltage. The designed circuits have been simulated using a $0.65{\mu}m$ n-well CMOS process parameters. The voltage-mode circuit has a temperature coefficient less than $48.0ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.21%/V for a temperature range of $-30^{\circ}C{\sim}130^{\circ}C$ and a VDD range of $3V{\sim}12V$. The current-mode circuit has a temperature coefficient less than $38.2ppm/^{\circ}C$ and a VDD coefficient less than 0.8%/V for $-30^{\circ}C{\sim}130^{\circ}C\;and\; 4V{\sim}12V$. The power consumption of the voltage-mode and current-mode circuits are $27{\mu}W\;and\;65{\mu}W$ respectively for 5V and $30^{\circ}C$. Measurement results show that the voltage-mode reference circuit has a VDD coefficient less than 0.63%/V for $30^{\circ}C{\sim}100^{\circ}C$ and has a temperature coefficient less than $490ppm/^{\circ}C\;for\;3V{\sim}6V$. The proposed reference circuits are simple and thus easy to design. The proposed current-mode reference circuit can be designed to generate a wide range of reference voltages.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.593-600
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• 2010

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

• ETRI Journal
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• v.34 no.6
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• pp.827-837
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• 2012

We propose a flow admission control (FAC) for setting up a wire-speed connection for new flows based on their negotiated bandwidth. It also terminates a flow that does not have a packet transmitted within a certain period determined by the users. The FAC can be used to provide a reliable transmission of user datagram and transmission control protocol applications. If the period of flows can be set to a short time period, we can monitor active flows that carry a packet over networks during the flow period. Such powerful flow management can also be applied to security systems to detect a denial-of-service attack. We implement a network processor called a flow management network processor (FMNP), which is the second generation of the device that supports FAC. It has forty reduced instruction set computer core processors optimized for packet processing. It is fabricated in 65-nm CMOS technology and has a 40-Gbps process performance. We prove that a flow router equipped with an FMNP is better than legacy systems in terms of throughput and packet loss.

• ETRI Journal
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• v.34 no.6
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• pp.950-953
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• 2012

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of $550{\mu}A/{\mu}m$ and $-376{\mu}A/{\mu}m$, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is $0.05{\mu}S$ and $1.2{\mu}S$ for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.127-132
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• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• ETRI Journal
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• v.38 no.4
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• pp.685-694
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• 2016

A surface micromachined piezoresistive pressure sensor with a novel internal substrate vacuum cavity was developed. The proposed internal substrate vacuum cavity is formed by selectively etching the silicon substrate under the sensing diaphragm. For the proposed cavity, a new fabrication process including a cavity side-wall formation, dry isotropic cavity etching, and cavity vacuum sealing was developed that is fully CMOS-compatible, low in cost, and reliable. The sensitivity of the fabricated pressure sensors is 2.80 mV/V/bar and 3.46 mV/V/bar for a rectangular and circular diaphragm, respectively, and the linearity is 0.39% and 0.16% for these two diaphragms. The temperature coefficient of the resistances of the polysilicon piezoresistor is 0.003% to 0.005% per degree of Celsius according to the sensor design. The temperature coefficient of the offset voltage at 1 atm is 0.0019 mV and 0.0051 mV per degree of Celsius for a rectangular and circular diaphragm, respectively. The measurement results demonstrate the feasibility of the proposed pressure sensor as a highly sensitive circuit-integrated pressure sensor.

• ETRI Journal
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• v.38 no.4
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• pp.654-664
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• 2016

This paper presents a transformer-based reconfigurable synchronous boost converter. The lowest maximum power point tracking (MPPT)-input voltage and peak efficiency of the proposed boost converter, 20 mV and 88%, respectively, were achieved using a reconfigurable synchronous structure, static power loss minimization design, and efficiency boost mode change (EBMC) method. The proposed reconfigurable synchronous structure for high efficiency enables both a transformer-based self-startup mode (TSM) and an inductor-based MPPT mode (IMM) with a power PMOS switch instead of a diode. In addition, a static power loss minimization design, which was developed to reduce the leakage current of the native switch and quiescent current of the control blocks, enables a low input operation voltage. Furthermore, the proposed EBMC method is able to change the TSM into IMM with no additional time or energy loss. A prototype chip was implemented using a $0.18-{\mu}m$ CMOS process, and operates within an input voltage range of 9 mV to 1 V, and an output voltage range of 1 V to 3.3 V, and provides a maximum output power of 37 mW.