• Journal of information and communication convergence engineering
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• v.8 no.6
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• pp.716-720
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• 2010

This paper proposes an effective fingerprint identification system with hardware block for thinning stage processing of a verification algorithm based on minutiae with 39% occupation of 32-bit RISC microprocessor cycle. Each step of a fingerprint algorithm is analyzed based on FPGA and ARMulator. This paper designs an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160{\times}192$ pixel array. The ZS algorithm is applied for a thinning stage. The logic is also synthesized in $0.35{\mu}m$ 4-metal CMOS process. The layout is performed based on an auto placement-routing and post-simulation is performed in logic level. The result is compared with a conventional one.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1372-1381
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• 2017

This paper presents a high-side switch driver IC capable of improving the current sensing accuracy and providing reverse battery protection. Power semiconductor switches used to replace relay switches are encumbered by two disadvantages: they are prone to current sensing errors and they require additional external protection circuits for reverse battery protection. The proposed IC integrates a gate driver and current sensing blocks, thus compensating for these two disadvantages with a single IC. A p-sub-based 90-V $0.13-{\mu}m$ bipolar-CMOS-DMOS (BCD) process is used for the design and fabrication of the proposed IC. The current sensing accuracy (error ${\leq}{\pm}5%$ in the range of 0.1 A-6.5 A) and the reverse battery protection features of the proposed IC were experimentally tested and verified.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.650-656
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• 2004

This paper presents block and timing diagrams of the DWA(data weighted averaging) to optimize a feedback time delay of the sigma-delta modulator. Through the Matlab modeling, the optimized coefficients of the integrators are obtained to design the modulator. And then the fully differential SC integrators, feedback DAC, 9-level quantizer, and DWA are designed by considering the nonideal characteristics of the modulator. The designed second-order multibit modulator is fabricated in a 0.35$\mu\textrm{m}$ CMOS process. The designed modulator achieves 73dB signal-to-noise ratio and 72dB dynamic range at 1.2Vp-p 585kHz input singal and 52.8MHz sampling frequency.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.191-197
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• 2005

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.727-731
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• 2005

Design and manufacturing process of a full color LED microdislay fabricated by standard CMOS technology and containing an array of aluminum / nanostructured porous silicon reverse biased light emitting Schottky diodes will be discussed. Being of a solid state construction, this microdisplays are cost-effective, thin and light in weight due to very simple device architecture. Its benefits include also super high resolution, wide viewing angles, fast response time and wide operating temperature range. The advantages of full integration of an LED-array and driving circuitry onto a Si-chip will be also discussed.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.82-87
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• 1997

Ion-Sensitive Field-Effect Transistors(ISFETs) with LPCVD silicon nitride as a sensitive gate were fabricated on the basis of a CMOS process. The silicon nitride was deposited directly on a poly silicon gate-electrode. Using a specially designed measuring cell, the hydrogen ions sensing properties of the ISFET in liquid could be investigated without any bonding or encapsulation. At first, th sensitivity was estimated by simualtions according to the site-binding theory and the experimental results were analysed and compared with simulated results. The measured dta were in good agreement with the simulated results. The silicon nitride based ISFET has good linearity evaluated from correlation factor ($\geq$0.9998) and a mean pH-sensitivity of 56.8mV/pH. The maximum hysteresis width between forward(pH=3\longrightarrowpH=11)- and backward(pH=11\longrightarrowpH=3) titration was 16.7mV at pH=6.54.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.1-6
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• 1997

This paper describes the design of a network interface controller (NIC) chip which is to be used to support a novel adaptive virtual cut-through routing method for parallel compute systems with direct (i.e., point-to-point) interconnection networks. The NIC chip is designed to provide the interface between a processing node constructed from commercially available microprocessors and another custom-designed router chip, which in turn performs the actual routing of packets to their respective destinations. The NIC, designed using a semi-full-custom VLSi design technique outperform traditional wormhole routing with a minimal amount of hardware overhead. The NIC design has been fully simulated and laid out using a 0.8$\mu\textrm{m}$ CMOS process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.83-87
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• 2003

In the present paper we suggested a parallel branch structure of aluminum spiral inductor for the use of RF integrated circuit at 1∼3 GHz. The inductor was implemented on p-type silicon wafer (5∼15Ω-cm) under the standard CMOS process and it showed a enhanced qualify(Q) factor by more than 10 % with no degradation of inductance. The effect of the structure modification on the Q factor and the inductance was scrutinized comparing with conventional spital inductors

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.140-150
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• 1995

A symbolic layout generator, called Flexible Module Generator (FMG), has been developed for transgorming a given CMOS circuit netlist into an optimized symbolic layout. Contrary to other conventional module generators which place transistors either in horizontal or in vertical direction, FMG places transittors in any hence can multiples of 90$^{\circ}$. This flexible layout style can maximize the diffusion sharing and hence can reduce the wire-length for both of area minimization and performance improvement. In FMG, transistors are initially randomly placed and then selected transistors are iteratively replaced using an optimization technique based on simulated evolution. Whenever a transistor is replaced, the affected nets are rerouted. Constraints on the shape, aspect ratio, and critical path delays are considered during the optimization process. Routing is performed by using a modified maze router on polysilicon, metal 1, and metal 2 interconnection layers. additional routing grids are added, if necessary, for complete routing. Unused rows or columns are removed after routing for area minimization. Experimental reasults show that FMG synthesizes satisfactory layouts.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.82-87
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• 2020

The comprehensive and physics-based compact noise models for advanced CMOS devices were presented. The models incorporate important physical effects in nanoscale MOSFETs, such as the low frequency correlation effect between the drain and the gate, the trap-related phenomena, and QM (quantum mechanical) effects in the inversion layer. The drain current noise model was improved by including the tunneling assisted-thermally activated process, the realistic trap distribution, the parasitic resistance, and mobility degradation. The expression of correlation coefficient was analytically described, enabling the overall noise performance to be evaluated. With the consideration of QM effects, the comprehensive low frequency noise performance was simulated over the entire bias range.