• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.355-362
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• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.81-85
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• 2003

The Bi-directional Wireless Capsule endoscope con sists of CMOS Image sensor, FPGA, LED, Battery, DC to DC Converter, Transmitter, Receiver and Antennas. The RF transmitter at 1.2GHz range is designed and fabricated with 10 mm(diameter)x1.6 mm(thickness) dimension considering the maximum permission exposure(MPE), system size, power consumption, linearity and modulation method. The fabricated RF receiver at 400MHz range can demodulate the external signals so as to control the behavior of CMOS image sensor. four LEDs and Transmitter.

• Journal of Sensor Science and Technology
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• v.25 no.5
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• Journal of Sensor Science and Technology
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• v.17 no.2
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• pp.114-119
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• 2008

Wide dynamic range active pixel sensor(APS) using a charge pump circuit has been designed by using 2-poly 4-metal $0.35{\mu}M$ standard CMOS technology. The structure of the proposed APS is similar to the structure of the conventional 3-Tr APS. The proposed unit pixel consists of one photodiode and three MOSFETs. Using a charge pump circuit, the dynamic range of the proposed APS is increased, compared to the conventional 3-Tr APS.

• Journal of the Korean Society for Precision Engineering
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• v.26 no.11
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• pp.12-19
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• 2009

• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.51-58
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• 2010

This paper proposes an edge adaptive color interpolation for an ultra-small HD-grade complementary metal-oxide semiconductor (CMOS) video sensor in camera phones that can process 720-p/30-fps videos. Recently, proposed methods with great image quality perceptually reconstruct the green component and then estimate the red/blue component using the reconstructed green and neighbor red and blue pixels. However, these methods require the bulky memory line buffers in order to temporally store the reconstructed green components. The edge adaptive color interpolation method uses seven or nine patterns to calculate the six edge directions. At the same time, the threshold values are adaptively adjusted by the sum of the color values of the selected pixels. This method selects the suitable one among the patterns using two flowcharts proposed in this paper, and then interpolates the missing color values. For verification, we calculated the peak-signal-to-noise-ratio (PSNR) in the test images, which were processed by the proposed algorithm, and compared the calculated PSNR of the existing methods. The proposed color interpolation is also fabricated with the 0.18-${\mu}m$ CMOS flash memory process.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.41-52
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• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.26-36
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• 2006

In this paper, we propose a cost-effective color filter may (CFA) demosaicing method for digital still cameras in which a single CCD or CMOS image sensor is used. Since a CFA is adopted, we must interpolate missing color values in the red, green and blue channels at each pixel location. While most state-of-the-art algorithms invest a great deal of computational effort in the enhancement of the reconstructed image to overcome the color artifacts, we focus on eliminating the color artifacts with low computational complexity. Using spatial correlation of the adjacent pixels, the edge-directional information of the neighbor pixels is used for determining the edge direction of the current pixel. We apply our method to the state-of-the-art algorithms which use edge-directed methods to interpolate the missing color channels. The experiment results show that the proposed method enhances the demosaiced image qualify from $0.09{\sim}0.47dB$ in PSNR depending on the basis algorithm by removing most of the color artifacts. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 12K, and five line memories are used.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.194-199
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• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.847-850
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• 2003

An Eye Ball Sensor (EBS) is a system that locates the point where the user gazes on. The conventional EBS using a CCD camera needs many peripherals, software computation causing high cost and power consumption. This paper proposes a compact EBS using smart CMOS Image Sensor (CIS) pixels. The proposed single chip EBS does not need any peripheral and operates at higher speed and lower cost than the conventional EBS. The test chip was designed and fabricated for 32$\times$32 smart CIS pixel array with a 0.35 um CMOS process occupying 5.3$\textrm{mm}^2$ silicon area.