• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.401-404
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• 2015

This paper proposes a high-performance in-loop filter in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. HEVC uses in-loop filter consisting of deblocking filter and SAO(Sample Adaptive Offset) to solve the problems of quantization error which causes image degradation. In the proposed in-loop filter encoder hardware architecture, the deblocking filter and SAO has a 2-level hybrid pipeline structure based on the $32{\times}32CTU$ to reduce the execution time. The deblocking filter is performed by 6-stage pipeline structure, and it supports minimization of memory access and simplification of reference memory structure using proposed efficient filtering order. Also The SAO is implemented by 2-statge pipeline for pixel classification and applying SAO parameters and it uses two three-layered parallel buffers to simplify pixel processing and reduce operation cycle. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 205K logic gates in TSMC 0.13um process. At 110MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 30fps in realtime.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.416-419
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• 2015

In this paper, we propose an effective design of transform hardware for real-time HEVC(High Efficiency Video Coding) encoder. HEVC encoder determines the transform mode($4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$) by comparing RDCost. RDCost require a significant amount of computation and time because it is determined by bit-rate and distortion which is computated via transform, quantization, dequantization, and inverse transform. This paper therefore proposes a new method for transform mode determination using sum of transform coefficient. Also, proposed hardware architecture is implemented with multiplexer, recursive adder/subtracter, and shifter only to derive reduction of the computation. Proposed method for transform mode determination results in an increase of 0.096 in BD-PSNR, 0.057 in BD-Bitrate, and decrease of 9.3% in encoding time by comparing HM 10.0. The hardware which is proposed is implemented by 256K logic gates in TSMC 130nm process. Its maximum operation frequency is 200MHz. At 140MHz, the proposed hardware can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.169-169
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• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.2
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• pp.397-407
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• 2015

In this paper, we designed 1 chip IC for 3-axis gyroscope and 3-axis accelerometer used for various IoT/M2M mobile devices such as smartphone, wearable device and etc. We especially focused on analysis of gyroscope noise and proposed new architecture for removing various noise generated by gyroscope MEMS and IC. Gyroscope, accelerometer and geo-magnetic sensors are usually used to detect user motion or to estimate moving distance, direction and relative position. It is very important element to designing a low noise IC because very small amount of noise may be accumulated and affect the estimated position or direction. We made a mathematical model of a gyroscope sensor, analyzed the frequency characteristics of MEMS and circuit, designed a low noise, compact and low power 1 chip 6-axis inertial sensor IC including 3-axis gyroscope and 3-axis accelerometer. As a result, designed IC has 0.01dps/${\sqrt{Hz}}$ of gyroscope sensor noise density.

• Korean Journal of Optics and Photonics
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• v.32 no.2
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• pp.68-78
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• 2021

A subminiature catadioptric omnidirectional optical system (SCOOS) with 2 mirrors, 6 plastic aspherical lenses, and an illumination system of 6 light emitting diodes, to observe the 360° panoramic image of the inner intestine, is optically designed and evaluated for a capsule endoscope. The total length, overall length, half field of view (HFOV), and F-number of the SCOOS are 14.3 mm, 8.93 mm, 51°~120°, and 3.5, respectively. The optical system has a complementary metal-oxide-semiconductor sensor with 0.1 megapixels, and an illumination system of 6 light-emitting diodes (LEDs) with 0.25 lm to illuminate on the 360° side view of the intestine along the optical axis. As a result, the spatial frequency at the modulation transfer function (MTF) of 0.3, the depth of focus, and the cumulative probability of tolerance at the Nyquist frequency of 44 lp/mm and MTF of 0.3 of the optimized optical system are obtained as 130 lp/mm, -0.097 mm to +0.076 mm, and 90.5%, respectively. Additionally, the simulated illuminance of the LED illumination system at the inner surface of the intestine within HFOV, at a distance of 15.0 mm from the optical axis, is from a minimum of 315 lx to a maximum of 725 lx, which is a sufficient illumination and visibility.

• Journal of Sensor Science and Technology
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• v.28 no.1
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• pp.41-46
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• 2019

In order to develop novel thermal imaging materials for microbolometer applications, $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ ($0.18{\leq}x{\leq}0.26$) thin films were fabricated using metal-organic decomposition. Effects of Cu content on the electrical properties of the annealed films were investigated. Spinel thin films with a thickness of approximately 100 nm were obtained from the $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ films annealed at $380^{\circ}C$ for five hours. The resistivity (${\rho}$) of the annealed films was analyzed with respect to the small polaron hopping model. Based on the $Mn^{3+}/Mn^{4+}$ ratio values obtained through x-ray photoelectron spectroscopy analysis, the hopping mechanism between $Mn^{3+}$ and $Mn^{4+}$ cations discussed in the proposed study. The effects of $Cu^+$ and $Cu^{2+}$ cations on the hopping mechanism is also discussed. Obtained results indicate that $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ thin films with low temperature annealing and superior electrical properties (${\rho}{\leq}54.83{\Omega}{\cdot}cm$, temperature coefficient of resistance > -2.62%/K) can be effectively employed in applications involving complementary metal-oxide semiconductor (CMOS) integrated microbolometer devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.755-758
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• 2014

In this paper, we propose effective Deblocking Filter hardware architecture for High Efficiency Video Coding encoder. we propose Deblocking Filter hardware architecture with less processing time, filter ordering for low area design, effective memory architecture and four-pipeline for a high performance HEVC(High Efficiency Video Coding) encoder. Proposed filter ordering can be used to reduce delay according to preprocessing. It can be used for realtime single-port SRAM read and write. it can be used in parallel processing by using two filters. Using 10 memory is effective for solving the hazard caused by a single-port SRAM. Also the proposed filter can be used in low-voltage design by using clock gating architecture in 4-pipeline. The proposed Deblocking Filter encoder architecture is designed by Verilog HDL, and implemented by 100k logic gates in TSMC $0.18{\mu}m$ process. At 150MHz, the proposed Deblocking Filter encoder can support 4K Ultra HD video encoding at 30fps, and can be operated at a maximum speed of 200MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].