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http://dx.doi.org/10.13089/JKIISC.2007.17.1.11

Fast RSA Montgomery Multiplier and Its Hardware Architecture  

Chang, Nam-Su (Korea University)
Lim, Dae-Sung (Korea University)
Ji, Sung-Yeon (Korea University)
Yoon, Suk-Bong (Dongeui University)
Kim, Chang-Han (Semyung University)
Publication Information
Journal of the Korea Institute of Information Security & Cryptology / v.17, no.1, 2007 , pp. 11-20 More about this Journal
Abstract
A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].
Keywords
Montgomery multiplication; Redundant binary adder; Signed-digit system;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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