• The Korean Journal of Financial Management
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• v.24 no.3
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• pp.29-62
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• 2007

We examine the methods to increase MBS values given parameters of default risks of individual mortgages and their correlation, and analyze the effects of these parameters on the efficiency of the methods. First, the values of MBS can be improved when they are comprised of low-correlation mortgages regardless of specific forms of investors' utility functions. Second, the values of MBS can also be raised even after their components mortgages are determined. More specifically, when investors' utilities are heterogeneous, CMO's of a less risky tranche and a riskier tranche are highly valued compared with pass-through securities of two identical tranches. When investors' utilities are homogeneous(risk averse), however, the latter meets the needs of investors better than the former does. Third, it can be shown that the efficiency of the methods in this paper is an increasing function of default risks of mortgage loans or of the correlation between them, and a decreasing function of the amount of the price fall of MBS when in default.

• Journal of the Korean Society of Industry Convergence
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• v.5 no.1
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.365-368
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• 2000

This paper describes image-rejection down conversion mixer for bluetooth application using 0.35u CMOS process. the proposed architecture is composed of LO phase shifter, mixer core, IF buffer, and IF phase shifter. IF phase shifter is designed using polyphase fillet. Simulation results show conversion gain = l0㏈, input 1㏈ compression point = -15.7㏈m. input third-order intercept point(IIP3) = -4.4㏈m, and image-rejection ratio = 37.8㏈, respectively, at 3V supply voltage, and 15.7㎃ current.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.577-580
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• 1998

This paper presents the characteristics of each MOS device and Bipolar device, then investigates about how these devices take effect on BiCMOS inverter from 300K to 470K. The turn-off and Logic swing characteristics of BiCMOS inverter are degraded by the electrical characteristics of the MOS to around 400K, but over that temperature enhanced by the characteristics of the Bipolar transistor.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2000.11a
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• pp.263-266
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• 2000

본 논문에서는 복잡한 카오스 신호를 발생시키는 HVPM(hyperchaotic volume preserving maps) 모델과 HVPM 모델의 구현회로를 제안한다. 랜덤한 카오스 신호를 발생시키기 위하여 3차원 이산시간(discrete-time) 연산과 비선형 사상(maps)으로 모듈러(modulus) 함수를 이용하여 하이퍼카오스 신호를 발생시킨다. 그리고 HVPM 모델은 여러 가지 시스템 파라미터들을 변화시키면 다양한 카오스 신호를 발생시킬 수 있으며, 출력되는 카오스 신호는 비주기성을 갖게 된다. 이러한 특징을 갖는 HVPM 모델의 회로 구현을 위하여 2단 N형의 함수를 CMOS와 선형 연산증폭기 및 비교기를 이용하여 보드상에서 구현하여, 다양한 하이퍼카오스 신호를 확인할 수 있었다.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.251-256
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• 1999

RF CMOS 집적회로 기술은 CMOS 기술의 급격한 발전과 더불어 최근 크게 주목 받고 있다. 이는 CMOS가 제공 할 수 대량생산 능력으로 인해 기존 RF IC의 저가격화뿐 아니라 미래의 복합.다기능 무선 멀티미디어 단말기 구현을 위란 single chip solution을 제공 할 수 있는 가능성이 가장 높기 때문이다. 본 논문은 먼저 개인 휴대 통신 단말기 시장을 전망해보고, 향후 전개될 다양한 무선서비스에 대응하기 위한 RF CMOS 집적회로의 소자 및 설계 기술개발 현황과 향후의 발전 전망을 기술한다.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.434-438
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• 2014

CMOS의 최종형태로써 Gate-All-Around(GAA) Silicon Nanowire(NW)가 각광받고 있다. 이 논문에서 NW FET(Field Effect Transistor)의 채널 길이와 NW의 폭과 같은 size에 따른 특성변화를 실제 실험 data와 NW FET 특성분석 simulation을 이용해서 비교해보았다. MOSFET(Metal Oxide Semiconductor Field Effect Transistor)의 소형화에 따른 쇼트 채널 효과(short channel effect)에 의한 threshold voltage($V_{th}$), Drain Induced Barrier Lowering(DIBL), subthreshold swing(SS) 또한 비교하였다. 이에 더하여, 기존의 상용툴로 NW를 해석한 시뮬레이션 결과와도 비교해봄으로써 NW의 size scaling에 대한 EDISON NW 해석 simulation의 정확도를 파악해보았다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.8
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• pp.330-334
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• 2003

A Temperature sensor system in which the digital output signal is proportional to the operating temperature is designed. The temperature sensor system is designed by using BiCMOS technology and consists of temperature sensor, voltage-to-frequency converter and counter. The proposed temperature sensor system has error less than $1^{\circ}C$ in the temperature range $-25^{\circ}C$ to $55^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.123-131
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• 2002

In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).