• Journal of Global Scholars of Marketing Science
• /
• v.16 no.2
• /
• pp.55-75
• /
• 2006

This study aims to identify the unknown essential condition to form the blue ocean market, in addition to the innovation of customer value which does not become a sufficient condition though it is one of the essential conditions to form a blue ocean market, and induce companies to take a firm foothold in the blue ocean market after going to the blue ocean market by segmenting the market after setting up appropriate strategies. On the basis of those goals of this study, we dealt with subjects like the problem of approaching the market that possesses factors of differentiated value innovation, the segmentation of value innovative market, the problem about the major variables that shed light on the character of blue ocean optical illusion market, the strategy for following companies to enter the market, which we applied to the actual analysis based on the investigation into the literature related to value innovation and blue ocean strategy, investigation into the actual cases and objective data. We analysed a domestic refrigerator market and a domestic chewing gum market as representative examples of durables and nondurables and segmented each market on a value innovation market. We discovered the blue ocean and the blue ocean's illusive market of the two markets. I've mentioned and studied the characters of those positively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.4
• /
• pp.292-301
• /
• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.9
• /
• pp.54-58
• /
• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Journal of the Korean Vacuum Society
• /
• v.19 no.2
• /
• pp.141-147
• /
• 2010

In this study, high-k oxide films like $Al_2O_3$, $TiO_2$, $HfO_2$ were deposited on Si, $SiO_2$/Si, GaAs wafers, and then the thermal conductivity was measured by using thermo-reflectance method which utilizes the reflectance variation of the film surface produced by the periodic temperature variation. The result shows that high-k oxide films with 50 nm thickness have high thermal conductivity of 0.80~1.29 W/(mK). Therefore, effectively dissipate the heat generated in the electric circuit such as CMOS memory device, and the heat transfer changes according to the micro grain size.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.10
• /
• pp.2509-2515
• /
• 2014

In this paper, the conventional vertical structure for VLSI circuits CMOS intend to improve the stress effects of active region and built-in threshold voltage. For these improvement, the proposed structure is shallow trench isolation of moat shape. We want to analysis the electron concentration distribution, gate bias vs energy band, thermal stress and dielectric enhanced field of thermal damage between vertical structure and proposed moat shape. Physically based models are the ambient and stress bias conditions of TCAD tool. As an analysis results, shallow trench structure were intended to be electric functions of passive as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage, are decreased the stress effects of active region. The fabricated device of based on analysis results data were the almost same characteristics of simulation results data.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.7
• /
• pp.822-828
• /
• 2019

An Augmented Reality(AR) provides virtual information with a real environment, and the processor needs to access the memory for the AR system. However, the processor has the heavy workload as the technology improvement leads to increase the size of data. We need a specific module to reduce the workload to overcome the limitation. In this paper, we propose a Direct Memory Access(DMA) controller displaying image instead of the processor. We implemented the proposed DMA controller on a Field Programmable Gate Array(FPGA) and demonstrated the functionality of the DMA controller based on an Avalon Memory Mapped(Avalon-MM) interface. Also, the DMA controller is fabricated by using Magnachip/Hynix 0.35um CMOS technology and verified the feasibility of the embedded system.

• KOREAN JOURNAL OF CROP SCIENCE
• /
• v.30 no.3
• /
• pp.229-235
• /
• 1985

Zoning of the agroclimatic regions was attempted based on the distribution of drought index, effective temperature, meteorological factors and their standard deviation and a climatic productivity derived from yield response of rice to temperature and sunshine hours. The meteorological data obtained from synoptic weather stations under the Central Meteorology Office and simple weather observatories under the Rural Development Administration at 155 locations throughout the country were computerized in the PDP11/70, RDA Computer Center, to analyze the climatic similarities among the locations, except the Jeju Island. The nineteen different agroclimatic regions were classified, ego the Taebaeg Mountainous Region. the Charyung Southern Plain Region, etc., and the climatic characteristics of the regions were identified.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.7 no.10
• /
• pp.895-903
• /
• 2017

Quantum Cellular Automata(QCA) is one of the proposed techniques as an alternative solution to the fundamental limitations of CMOS. QCA has recently been extensively studied along with experimental results, and is attracting attention as a nano-scale size and low power consumption. Although the XOR gates proposed in the previous paper can be designed using the minimum area and the number of cells, there is a disadvantage that the number of added cells is increased due to the stability and the accuracy of the result. In this paper, we propose a gate that supplement for the drawbacks of existing XOR gates. The XOR gate of this paper reduces the number of cells by arranging AND gate and OR gate with square structure and propose a half-adder by adding two cells that serve as simple inverters using the proposed XOR gate. Also This paper use QCADesginer for input and result accuracy. Therefore, the proposed half-adder is composed of fewer cells and total area compared to the conventional half-adder, which is effective when used in a large circuit or when a half - adder is needed in a small area.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.107-116
• /
• 2009

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.17 no.2
• /
• pp.69-74
• /
• 2007

[ $0.6Pb(Sc_{1/2}Ta_{1/2})O_3-0.4PbTiO_3$ ] (hereafter PSTT) ceramics were prepared by the molten salt synthesis (MSS) method using KCI as a flux. Formation of perovskite phase was investigated by a differential thermal analysis (DTA) and X-ray diffraction (XRD) analysis in the temperature range from $600^{\circ}C$ to $850^{\circ}C$. A 92% perovskite phase was synthesized at $750^{\circ}C$ for 2 hrs using the MSS method, while 82% perovskite phase was synthesized at $850^{\circ}C$ for 4ks using the calcining of mixed oxide (CMO) method. This result could be due to the improvement in reactivity of $Sc_2O_3$ by melting of KCI. The MSS specimen sintered at $1,100^{\circ}C$ for 4hrs showed a dielectric constant of 11,200, a remnant polarization of $13.5{\mu}C/cm^2$ and a coercive field of 10.198 kV/cm, which was discussed in view of the microstructure.