• Journal of Life Science
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• v.32 no.11
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• pp.833-840
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• 2022

Chronic inflammation has been shown to be closely associated with tumor development and progression. Nuclear factor kappa B (NF-κB) is composed of a family of five transcription factors. NF-κB signaling plays a crucial role in the inflammatory response and is often found to be dysregulated in various types of cancer, making it an attractive target in cancer therapeutics. In this study, CDC-like kinase 3 (CLK3) was identified as a novel kinase that regulates the NF-κB signaling pathway. Our data demonstrate that CLK3 inhibits the canonical and non-canonical NF-κB pathways. Luciferase assays following the transient or stable expression of CLK3 indicated that this kinase inhibited NF-κB activation mediated by Tumor necrosis factor-alpha (TNFα) and Phorbol 12-myristate 13-acetate (PMA), which are known to activate NF-κB signaling via the canonical pathway. Consistent with data on the ectopic expression of CLK3, CLK3 knockdown using shRNA constructs increased NF-κB activity 1.5-fold upon stimulation with TNFα in HEK293 cells compared with the control cells. Additionally, overexpression of CLK3 suppressed the activation of this signaling pathway induced by NF-κB-inducing kinase (NIK) or CD40, which are well-established activators of the non-canonical pathway. To further examine the negative impact of CLK3 on NF-κB signaling, we performed Western blotting following the TNFα treatment to directly identify the molecular components of the NF-κB pathway that are affected by this kinase. Our results revealed that CLK3 mitigated the phosphorylation/activation of transforming growth factor-α-activated kinase 1 (TAK1), inhibitor of NF-κB kinase alpha/beta (IKKα/α), NF-κB p65 (RelA), NF-κB inhibitor alpha (IκBα), and Extracellular signal-regulated kinase 1/2-Mitogen-activated protein kinase (ERK1/2-MAPK), suggesting that CLK3 inhibits both the NF-κB and MAPK signaling activated by TNFα exposure. Further studies are required to elucidate the mechanism by which CLK3 inhibits the canonical and non-canonical NF-κB pathways. Collectively, these findings reveal CLK3 as a novel negative regulator of NF-κB signaling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.72-83
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• 2002

In this paper, a novel low-power VLSI system architecture was proposed. By exploiting software control of supply voltages, it simplifies hardware implementation, reduces power consumption efficiently, and avoids complicated interface circuits. The proposed architecture models clock frequency-supply voltage relationship by software modelling, enables individual control of supply voltages for all chips in the system, and restricts clock frequency to discrete levels of $f_{CLK}$, $f_{CLK}$2, $f_{CLK}$3... where $f_{CLK}$ is the master clock frequency A prototype system was implemented by modifying off-the-shelf microprocessor evaluation board and adding simple discrete devices such as level shifters and voltage switches. It was measured that the power consumption was reduced from 0.58W to 0.12W in the Prototype system. system.

• BMB Reports
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• v.49 no.11
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• pp.587-589
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• 2016

The circadian clock system enables organisms to anticipate the rhythmic environmental changes and to manifest behavior and physiology at advantageous times of the day. Transcriptional/translational feedback loop (TTFL) is the basic feature of the eukaryotic circadian clock and is based on the rhythmic association of circadian transcriptional activator and repressor. In Drosophila, repression of dCLOCK/CYCLE (dCLK/CYC) mediated transcription by PERIOD (PER) is critical for inducing circadian rhythms of gene expression. Pacemaker neurons in the brain control specific circadian behaviors upon environmental timing cues such as light and temperature cycle. We show that amino acids 657-707 of dCLK are important for the transcriptional activation and the association with PER both in vitro and in vivo. Flies expressing dCLK lacking AA657-707 in $Clk^{out}$ genetic background, homologous to the mouse Clock allele where exon 19 region is deleted, display pacemaker-neuron-dependent perturbation of the molecular clockwork. The molecular rhythms in light-cycle-sensitive pacemaker neurons such as ventral lateral neurons ($LN_vs$) were significantly disrupted, but those in temperature-cycle-sensitive pacemaker neurons such as dorsal neurons (DNs) were robust. Our results suggest that the dCLK-controlled TTFL diversify in a pacemaker-neuron-dependent manner which may contribute to specific functions such as different sensitivities to entraining cues.

• Journal of Photoscience
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• v.9 no.2
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• pp.240-242
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• 2002

In Drosophila melanogaster, it is known that the circadian clock consists of an autoregulatory feedback loop, which includes so-called clock genes, such as per, tim, dClk and cyc and produces periodical expression of per. It is recently suggested, however, that the circadian oscillation without the rhythmical expression of per is involved in the regulation of circadian locomotor rhythms. In the present study, we examined the existence and the property of the possible per-less oscillation using arrhythmic clock mutant flies carrying per$^{01}$, tim$^{01}$, dClk$^{Jrk}$ or cyc$^{01}$. When temperature cycles consisting of 25$^{\circ}$Ｃ and 30$^{\circ}$Ｃ with varying periods (T = 8~32 hr) were given, they showed rhythms synchronizing with the given cycle under constant darkness (DD). per$^{01}$ and tim$^{01}$ flies always showed a peak around 7 hr after the onset of thermophase irrespective of Ts of temperature cycles, while dClk$^{Jrk}$ and cyc$^{01}$ flies did not. In addition, several days were necessary to establish a clear temperature entrainment in per$^{01}$ and tim$^{01}$ flies, when they were transferred from a constant temperature to a temperature cycle under DD. These results suggest that per$^{01}$ and tim$^{01}$ flies have a temperature-entrainable weak oscillatory mechanism. The fact that dClk$^{Jrk}$ and cyc$^{01}$ flies did not show any sign of the endogenous oscillation suggests that the per-less oscillatory mechanism may require CLK and CYC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.600-603
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• 2008

In this paper, a new circuit design named memory-in-pixel for low power consumption of the liquid crystal display (LCD) is presented. Since each pixel has a memory, it is able to express 8 color grades using the data saved in the memory without the operation of the gate and source driver ICs so that it can reduce the power consumption of the LCD panel. A memory circuit consists of modified S-R flip-flop (NAND-type) implemented in the pixel, which can supply AC bias for operating the liquid crystal (LC) with the interlocking clocks (CLK_A and CLK_B). This circuit is more complex than the inverter-type memory circuit, but it has lower power consumption of approximately 50% than the circuit. We have investigated the power consumption both NAND and inverter-type memory circuit using a Smart SPICE for the resolution of $96{\times}128$. The estimated power consumption of the inverter-type memory was about 0.037mW. On the other hand, the NAND-type memory showed power consumption of about 0.007mW.

• ETRI Journal
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• v.26 no.6
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• pp.669-672
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• 2004

To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters $C_g=C_T=C_{clk}=1\;aF,\;R_T=5\;M{\Omega},\;V_{clk}=40\;mV$, and $V_{in}=20\;mV$. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.671-672
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• 2006

Recently Communication with using IrDA is bing used in various fields. In this paper I designed a receiver by fabricating hardware that used to be fabricated through software, so anyone who don't have knowledge on IrDA can receive Ir Signal easily. This receiver can communicate with CPU through 8 bit data and 3 bit address. Also this receiver can use user-needed CLK because this receiver embodied 16 bit CLK Prescaler.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.1
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• pp.88-94
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• 2005

This paper presents the design and implementation of a receiver operating between a rotary machine encoder and DSP. The receiver connects with the encoder using 1 bit serial data and DSP using 16 bits bus line. The receiver and encoder use the different operating frequency each other. We suggest a new apparatus and method of synchronized code for header detection in 1bit serial communication. The system operating frequency can be changed into 20MHz or 60MHz by using the external port such as 'clk_select'.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.12
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• pp.991-997
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• 2013

A new frequency tuning scheme and a transconductor with a wide tuning range and low harmonic distortion is presented. This frequency tuning technique is based on the relationship between the time-constant and the elapsed times in charging a capacitor up to a certain level. Its structure is as simple as that of a conventional tuning scheme using a VCF(Voltage-Controlled Filter) and it does not need a pure sine wave but uses a CLK(Clock) pulse as a reference signal, which is easily obtained from on-chip system clocks or external X-tal oscillators. When a certain reference CLK is given, without complex capacitor arrays the pole frequency of the filter can be controlled continuously in the frequency domain. Simulation results are presented to confirm the operation of the proposed approach.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.15-19
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• 2011

We have proposed a maximum power point tracking (MPPT) circuit for thermoelectric generator (TEG) using a Boost converter. The key point of the proposed MPPT circuit is that the duty ratio of the boost converter automatically moves to Maximum Power Point by comparing of consecutive sampling voltage using two comparators. From the simulation results, we showed that the proposed circuit can find the maximum power point within 2 CLK periods and to generate optimal PWM signal within 3 CLK periods. The proposed MPPT circuit was designed by using a CMOS 0.18 um process, and it is now on the fabrication.