• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.399-405
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• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.7
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• pp.678-685
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• 2013

In this paper, we propose a design of dual-band patch antennas for Global Positioning System(GPS) applications, and the designed antenna is used as an individual element of GPS arrays. A low distortion and a high isolation of the array are achieved by adjusting rotating angles of each array element. The antenna consists of two radiating patches that operate in the GPS $L_1$ and $L_2$ bands, and the two ports feeding network with a hybrid chip coupler is adopted to achieve a broad circular polarization(CP) bandwidth. The rotating angles of each antenna element are varied with four directions(${\phi}=0^{\circ}$, ${\phi}=90^{\circ}$, ${\phi}=180^{\circ}$, ${\phi}=270^{\circ}$) in order to minimize the pattern distortion and maximize the isolation among array elements. The measurement shows bore-sight gains of 0.3 dBic($L_1$) and -1.0 dBic($L_2$) for the center element. Bore-sight gains of 1.6 dBic($L_1$) and 1.0 dBic($L_2$) are observed for the edge element. This results demonstrate that the proposed antenna is suitable for GPS array applications.

• Journal of Biomedical Engineering Research
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• v.19 no.5
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• pp.477-486
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• 1998

In this paper, we implemented the urine analysis system capable of measuring a qualitative and semi-quantitative and assay using strip. The analysis algorithm of urine analysis was adopted a fuzzy logic-based classifiers that was robust to external error factors such as temperature and electric power noises. The spectroscopic properties of 9 pads In a strip were studied to developing the urine analysis system was designed for robustnesss and stability. The urine analysis system was consisted of hardware and software. The hardware of the urine analysis system was based on one-chip microprocessor, and Its peripherals which composed of optic modulo, tray control, preamplifier, communication with PC, thermal printer and operating status indicator. The software of the urine analysis system was composed of system program and classification program. The system program did duty fort system control, data acquisition and data analysis. The classification program was composed of fuzzy inference engine and membership function generator. The membership function generator made triangular membership functions by statical method for quality control. Resulted data was transferred through serial cable to PC. The transferred data was arranged and saved be data acquisition program coded by C+ + language. The precision of urine analysis system and the stability of fuzzy classifier were evaluated by testing the standard urine samples. Experimental results showed a good stability states and a exact classification.

• Korean Journal of Environmental Agriculture
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• v.22 no.4
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• pp.261-265
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• 2003

In order to examine the difference in processing quality of potato tubers among localities, chemical properties of soils were analyzed and climatic conditions were investigated. Potatoes (Solanum tuberosum L.) were grown at seven localities of Korea during two years from 1994 to 1995. Soil samples and tubers were obtained from 2 to 3 commercial farms per locality with 10 days interval from 70 days before harvesting. As the result of that, higher correlation in processing quality was found with organic material content among soil conditions. On the climatic conditions, minimum temperature and sunshine hours during the period from 30 to 11 days before harvesting exhibited highly significant negative correlations with all quality parameters except reducing sugar content. Additionally, regression equations based on the observed level of these factors showed the relatively high coefficients of determination for dry matter content and chip color. To produce higher quality potatoes for processing, therefore, climatic conditions such as minimum temperature and sunshine hour and soil condition such as organic matter content have to be considered before the selection of areas or fields.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1125-1134
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• 2011

In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.444-447
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• 2011

In this paper, parallel IT(inverse transform) architecture and IQ(inverse quantization) architecture with common operation unit for the H.264/AVC decoder are proposed. By using common operation unit, the area cost and computational complexity of IQ are reduced. In order to take four execution cycles to perform IT, the proposed IT architecture has parallel architecture with one horizontal DCT unit and four vertical DCT units. Furthermore, the execution cycles of the proposed architecture is reduced to five cycles by applying two state pipeline architecture. The proposed architecture is implemented to a single chip by using Magnachip 0.18um CMOS technology. The gate count of the proposed architecture is 14.3k at clock frequency of 13MHz and the area of proposed IQ is reduced 39.6% compared with the previous one. The experimental result shows that execution cycle the proposed architecture is about 49.09% higher than that of the previous one.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.423-424
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• 2011

This paper has proposed a 920 MHz RF front-end for IEEE 802.15.4g SUN (Smart Utility Network) systems. The proposed 920 MHz RF front-end consists of a driver amplifier, a low noise amplifier, and a RF switch. In the TX mode, the driver amplifier has been designed as a single-ended topology to remove a transformer which causes a loss of the output power from the driver amplifier. In addition, a RF switch is located in the RX path not the TX path. In the RX mode, the proposed low noise amplifier can provide a differential output signal when a single-ended input signal has been applied to. A LC resonant circuit is used as both a load of the drive amplifier and a input matching circuit of the low noise amplifier, reducing the chip area. The proposed 920 MHz RF Front-end has been implemented in a 0.18-um CMOS technology. It consumes 3.6 mA in driver amplifier and 3.1 mA in low noise amplifier from a 1.8 V supply voltage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.345-352
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• 2017

In this paper, a unified potentiostat which can measure the current of both $O_2$-based and $H_2O_2$-based blood glucose sensors with low supply voltage of 1.0V has been designed and verified by simulations and measurements. Potentiostat is composed of low-voltage operational transconductance amplifier, cascode current mirrors and mode-selection circuits. It can measure currents of blood glucose chemical reactions occurred by $O_2$ or $H_2O_2$. The body of PMOS input differentional stage of the operational transconductance amplifier is forward-biased to reduce the threshold voltage for low supply voltage operation. Also, cascode current mirror is used to reduce current measurement error generated by channel length modulation effects. The proposed low-voltage potentiostat is designed and simulated using Cadence SPECTRE and fabricated in Magnachip 0.18um CMOS technology with chip size of $110{\mu}m{\times}60{\mu}m$. The measurement results show that consumption current is maximum $46{\mu}A$ at supply voltage of 1.0V. Using the persian potassium($K_3Fe(CN)_6$) equivalent to glucose, the operation of the fabricated potentiostat was confirmed.

• Journal of Sensor Science and Technology
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• v.6 no.5
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• pp.385-391
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• 1997

An objection of this study is to develop a measuring circuit of a gauge using radioisotope for compaction control. The gauge developed in this study makes use of radioisotope with the activity exempted from domestic atomic law and consists of measuring circuits for gamma-rays and thermal neutrons, a high voltage supply unit, and a microprocessor. To obtain meaningful numbers of pulse counts, parallel five and two circuits are provided for gamma-rays and thermal neutrons, respectively. Being simple in electrical characteristics of G-M detector for gamma-rays, pulses are counted through only a shaping circuit. Very small pulses generated from He- 3 proportional detector for thermal neutrons are amplified to the maximum of 50 [dB] and a window comparator accepts only pulses with meaning. To minimize effects of natural environmental radiation and electrical noise, circuits are electrostatically shielded and pulses made by ripples are eliminated by taking frequency of high voltage supplied to the circuit and pulse height of ripples into consideration. One-chip microprocessor is applied to process various counts, results are stored and the gauage is made capable to communicate with PC. Enough and meaningful numbers of pulses are counted with the prototype gauage for compaction control.