• Journal of IKEEE
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• v.19 no.3
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• pp.424-430
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• 2015

This paper proposes an optical cryptography application to 2-D page-oriented data based on CFB(Cipher Feedback) mode algorithm. The proposed method uses a free-space optical interconnected dual-encoding technique which performs XOR logic operations in order to implement 2-D page-oriented data encryption. The proposed method provides more enhanced cryptosystem with greater security strength than the conventional CFB block mode with 1-D encryption key due to the huge encryption key with 2-D arrayed page type. To verify the proposed method, encryption and decryption of 2-D page data and error analysis are carried out by computer simulations. The results show that the proposed CFB optical encryption system makes it possible to implement stronger cryptosystem with massive data processing and long encryption key compared to 1-D block method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1419-1424
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• 2005

This paper suggests a new cipher mode of operation which can recover cryptographic synchronization. First, we study the typical cipher modes of operation, especially focused on cryptographic synchronization problems. Then, we suggest a statistical cipher-feedback mode of operation. We define the error sources mathmatically and simulate propagation errors caused by a bit insertion or bit deletion. In the simulation, we compare the effects of changing the synchronization pattern length and feedback key length. After that, we analyze the simulation results with the calculated propagation errors. finally. we evaluate the performance of the statistical cipher-feedback mode of operation and recommand the implementation considerations.

• Current Optics and Photonics
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• v.5 no.2
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• pp.155-163
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• 2021

We propose a novel optical encryption scheme for cipher-feedback-block (CFB) mode, capable of encrypting two-dimensional (2D) page data with the use of two-step phase-shifting digital interferometry utilizing orthogonal polarization, in which the CFB algorithm is modified into an optical method to enhance security. The encryption is performed in the Fourier domain to record interferograms on charge-coupled devices (CCD)s with 256 quantized gray levels. A page of plaintext is encrypted into digital interferograms of ciphertexts, which are transmitted over a digital information network and then can be decrypted by digital computation according to the given CFB algorithm. The encryption key used in the decryption procedure and the plaintext are reconstructed by dual phase-shifting interferometry, providing high security in the cryptosystem. Also, each plaintext is sequentially encrypted using different encryption keys. The random-phase mask attached to the plaintext provides resistance against possible attacks. The feasibility and reliability of the proposed CFB method are verified and analyzed with numerical simulations.

• Journal of the Korean Society for Heat Treatment
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• v.10 no.4
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• pp.232-236
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• 1997

A rectangular type circulating fluidized bed (CFB) with an internal nozzle and two partition walls was proposed. In this modified CFB, an internal nozzle and two slanted partition walls were additionally set in the riser. This cold mode apparatus was made of acrylic resin; the riser was 1500mm high and $1000{\times}1000mm^2$ in the cross sectional area, the internal nozzle was 200mm high and 10mm in the inner diameter, and the partition wall was 7mm thick. Glass beads of $91{\mu}m$ in the mean diameter were employed as bed materials. In the cold mode by using the proposed CFB with an internal nozzle, it was possible to change the particle hold up by changing the gas flow ratio of the nozzle to the total(Qn/Qt). It was found that the inflection point which devided the bed structure between the dense and the dilute phase in the riser varied with Qn/Qt.

• Journal of the Korean Society for Heat Treatment
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• v.6 no.4
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• pp.243-248
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• 1993

A Circulating Fluidized-Bed (CFB) with an internal nozzle and a partition wall was proposed. The technique of fluidization is related to operations first used commercially in the fields of metallurgical and mechanical engineering such as the heat treatment of metals and power station combustors. In the modified CFB, an internal nozzle and a partition wall were additionally set in the main bed. This cold mode CFB apparatus made of acrylic resin; the main bed is 1,500mm high and 100mm in the inner diameter, the internal nozzle is 130mm high and 10mm in the inner diameter, and the partition wall is 7mm thick and 100mm in the diameter. Glass beads of $89{\mu}m$ in the mean diameter were employed as bed materials.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.103-107
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• 2007

This paper represents a forgery attack on new authenticated encryption mode $NAE^{[1]}$ which was proposed at JCCI 2003. NAE is a new authenticated encryption mode which is combined with CFB mode and CTR mode. And it provides confidentiality. In this paper, we show that it is possible to make a valid ciphertext-tag pair only by modifying a ciphertext.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.89-96
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• 2003

In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.333-337
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• 2006

Symmetric block ciper algorithm consists of a chains of operations such as permutation and substitution. There exists four kinds of operation mode, CBC, ECB, CFB, and OFB depending on the operation paradigm. Since the final ciper text is obtained through the many rounds of operations, it consumes much time. This paper proposes a pipelined design methodology which can improve the speed of crypto operations in ECB mode. Because the operations of the many rounds are concatenated in serial and executed concurrently, the overall computation time can be reduced significantly. The experimental result shows that the method can speed up the performance more than ten times.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.