Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.06b
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- Pages.169-172
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- 2000
VLSI Design of Cryptographic Processor for SEED and Triple DES Encryption Algorithm
SEED 와 TDES 암호 알고리즘을 구현하는 암호 프로세서의 VLSI 설계
Abstract
This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25
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