• The Bulletin of The Korean Astronomical Society
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• v.38 no.1
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• pp.71.1-71.1
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• 2013

한국천문연구원은 우주물체 전자광학 감시체계 기술개발 사업을 통해 자국위성의 추적감시를 위해 0.5m 광시야 감시관측소 국제 네트워크(OWL : Optical Wide-Field patroL)를 구축할 예정이다. OWL 시스템의 설계 검증을 위해 시험모델을 개발하였고, 연구소 내에 테스트베드에 설치하여 종합적인 테스트를 수행하고 있다. 2012년 11월 상세설계 검토회의(CDR)를 수행하여 해외 설치할 서브시스템들의 설계를 확정 하였다. 현재 테스트 베드에서는 마운트와 컨트롤 시스템의 성능을 시험하기위해 10인치 RC 대체 경통으로 테스트 관측을 수행하였고, 3월에 납품한 proto-type 경통을 부착하여 시험관측 중에 있다. 시험 관측으로 획득한 영상들과 시스템의 개발 진행사항을 논의 하고자 한다.

• The Journal of Korean Academy of Orthopedic Manual Physical Therapy
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• v.15 no.2
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• pp.44-49
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• 2009

Purpose : The purpose of this study was to evaluate the incidence and mortality for hip fracture in the elderly in Jeju-do. Methods : We enrolled 254 cases among 318 patients older than 50 years of age with a hip fracture during two years period(2003-2004). We investigated the incidence and mortality during follow up 3~4 years period until December 31, 2007. Results : The crude incidences of hip fracture the age group ${\geq}50$ years were 141(11.2/10,000) in 2003, 177(13.6/10,000) in 2004, and 249(17.0/10,000), 69(6.3/10,000) for women and men, respectively. The mean age of them was 78.3 years, male was 69(21.7%), female was 249(78.3%) among 318 patients. Survivor was in the 146(57.5%), death was in the 108(42.5%) among 254 cases period for follow up. In the death group, activity was significantly lower at the time of post-fracture 3(p=0.013), 6(p=0.000), and 12 months(p=0.000). The mortality of hip fracture and crude death rate(CDR) were 108(42.5%, n=254), 11,884(1.7%, n=675,889) in 2003~2007 in Jeju. Conclusion : Developing and applying a variety of activity programs that increase activity in post-fracture may improve activities of daily living, reduce burden of family and society, be useful in improving the quality of life and ultimately lower the mortality.

• Journal of Korean Society for Quality Management
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• v.42 no.3
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• pp.279-290
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• 2014

Purpose: The purpose of this study is to propose adoption of QFD and Stage-gate in order to analyze the quality of korea defense system. Methods: Drawing change data of initial production phase in korea defense system were anlayzed and a practical method was proposed. Results: The results of this study are as follows; Off line Quality Control should be introduced in development phase. Specially, in case of defense system, the best method is QFD(Quality Function Deployment) and Stage-gate process. At first, QFD 1 step defines product planning from VOC(Voice Of Customer), QFD 2 step specifies part planning from product planning, QFD 3 step defines process planning from part planning, QFD 4 step defines production planning from previous process planning. Secondly, Stage-gate process is adopted. This study is proposed 5 stage-gate in case of korea defense development. Gate 1 is located after SFR(System Function Review), Gate 2 is located after PDR(Preliminary Design Review), Gate 3 is located after CDR(Critical Design Review), Gate 4 is located after TRR(Test Readiness Review) and Gate 5 is located before specification documentation submission. Conclusion: Off line QC(Quality Control) in development phase is necessary prior to on line QC(Quality Control) in p roduction phase. For the purpose of off line quality control, QFD(Quality Function Deployment) and Stage-gate process can be adopted.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.28 no.2
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• pp.387-413
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• 1998

Image resampling is of particular interest in digital radiology. When resampling an image to a new set of coordinate, there appears blocking artifacts and image changes. To enhance image quality, interpolation algorithms have been used. Resampling is used to increase the number of points in an image to improve its appearance for display. The process of interpolation is fitting a continuous function to the discrete points in the digital image. The purpose of this study was to determine the effects of the seven interpolation functions when image resampling in digital periapical images. The images were obtained by Digora, CDR and scanning of Ektaspeed plus periapical radiograms on the dry skull and human subject. The subjects were exposed to intraoral X-ray machine at 60kVp and 70 kVp with exposure time varying between 0.01 and 0.50 second. To determine which interpolation method would provide the better image, seven functions were compared; (1) nearest neighbor (2) linear (3) non-linear (4) facet model (5) cubic convolution (6) cubic spline (7) gray segment expansion. And resampled images were compared in terms of SNR(Signal to Noise Ratio) and MTF(Modulation Transfer Function) coefficient value. The obtained results were as follows ; 1. The highest SNR value(75.96dB) was obtained with cubic convolution method and the lowest SNR value(72.44dB) was obtained with facet model method among seven interpolation methods. 2. There were significant differences of SNR values among CDR, Digora and film scan(P<0.05). 3. There were significant differences of SNR values between 60kVp and 70kVp in seven interpolation methods. There were significant differences of SNR values between facet model method and those of the other methods at 60kVp(P<0.05), but there were not significant differences of SNR values among seven interpolation methods at 70kVp(P>0.05). 4. There were significant differences of MTF coefficient values between linear interpolation method and the other six interpolation methods (P< 0.05). 5. The speed of computation time was the fastest with nearest -neighbor method and the slowest with non-linear method. 6. The better image was obtained with cubic convolution, cubic spline and gray segment method in ROC analysis. 7. The better sharpness of edge was obtained with gray segment expansion method among seven interpolation methods.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.97-103
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• 2014

In this paper, a clock-data recovery using a 1/8-rate phase detector is proposed. The use of a conventional full or half-rate phase detector requires relatively higher frequency of a recovered clock, which is a burden on the design of a sampling circuit and a VCO. In this paper, a 1/8-rate phase detector is used to lower the frequency of the recovered clock and a linear equalizer is used as a input circuit of a phase detector to reduce the jitter of the recovered clock. A test chip fabricated in a 0.13-${\mu}m$ CMOS process is measured at 1.5-GHz for a 3-Gb/s PRBS input and 1.2-V power supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.552-560
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• 2017

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

• The Journal of Korean Society for Neurotherapy
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• v.22 no.3
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• pp.37-42
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• 2018

Purpose. The purpose of this study was to determine the relationship between sleep quality and cognitive function, depression, and institutionalized elderly activity. The goal is to improve the quality of life through early intervention in the sleeping problems of the elderly hospitalized in the nursing home. Method Twentythree patients who were diagnosed with CDR (clinical dementia grade) 0.5 ~ 2 stages by a psychiatrist from September 3 to 30, 2017 were measured for sleep status, depression, cognitive function and activities of daily living at the same time once a day. The collected data were analyzed using SPSS (v.21, IBM, USA) program. Results The correlation between sleep status and cognitive function, depression, and activities of daily living was not statistically significant, and there was a moderate correlation between cognitive function and depression. Conclusion The results of this study suggest that the development and application of a program that activates the cognitive function that is institutionalized with a positive correlation between cognitive function and depression will be effective in decreasing depression in the elderly patients hospitalized in the nursing home.

• ETRI Journal
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• v.30 no.2
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• pp.268-274
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• 2008

This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.594-600
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• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.