• 정보처리학회논문지C
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• 제8C권5호
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• pp.657-666
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• 2001

본 논문에서는 글로벌 캐리어들이 고객 중심으로 음성 트래픽을 효율적으로 처리 및 관리할 수 있도록 CDR을 이용하여 음성 트래픽 관리 항목들을 제안하였으며, 관리 항목을 산출하기 위한 계산 수식들을 정의하였다. 이러한 관리 항목들을 웹 인터페이스 모듈, 분석 모듈, 데이터 수집 모듈, 데이터베이스 관리 모듈로 분리하여 시스템을 설계하였으며 웹 기술을 이용하여 시스템을 구현함으로써 가용성 및 사용의 편의성을 높였다. 또한, 규정된 관리 항목의 유효성을 검증하기 위하여 실제로 글로벌 캐리어에 의해 수집된 CDR을 바탕으로 관리 항목들을 실험하였다. 제안된 웹 기반 음성 트래픽 관리 시스템은 글로벌 캐리어들에게 네트워크 정보 수집, 장애 판단 및 원인 해결, 고객의 성향 분석을 통한 보다 질 높은 서비스 제공 등 도움을 줄 것으로 기대된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• 대한전자공학회논문지SD
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• 제45권2호
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• pp.130-134
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• 2008

본 논문에서는 1/4-레이트 기법을 사용한 클록 데이터 복원회로를 제안하였다. 제안한 클록 데이터 복원회로를 사용함에 따라 VCO의 발진 주파수를 낮추므로 고속 동작에 유리하다. 제안된 클록 데이터 복원회로는 기존 클록 데이터 복원회로 보다 낮은 지터 특성과 넓은 풀인(pull-in) 범위를 갖는다. 제안된 클록 데이터 복원회로는 1/4-레이트 뱅-뱅 형태의 오버샘플링 위상 검출기, 1/4-레이트 주파수 검출기, 2개의 전하펌프 회로와 저역 통과 필터 그리고 링 VCO회로로 구성되어 있다. 제안된 클록 데이터 복원회로는 $0.18{\mu}m$ 1P6M CMOS 공정으로 설계되었고, 칩 면적과 전력 소모는 $1{\times}1mm^2$, 98 mW 이다.

• 한방재활의학과학회지
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• 제30권2호
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• pp.105-123
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• 2020

Objectives This study was conducted to verify the effectiveness of east-west integrative rehabilitation therapy on activity of daily living and cognitive functional recovery in stroke patients by comparing with integrative rehabilitation therapy group and conventional rehabilitation therapy group in a single institution. Methods The medical records of 106 stroke patients hospitalized in Department of Rehabilitation Medicine, Dongguk University Bundang Oriental Hospital from January 1, 2017 to February 28, 2019 were reviewed. After screening and dividing it into conventional rehabilitation (CR) group and integrative rehabilitation (IR) group, Korean version of Modified Barthel Index (K-MBI), functional independence measure (FIM), clinical dementia rating-sum of boxes (CDR-SB) were statistically analyzed. Results IR group showed significant improvement in K-MBI, FIM, and CDR-SB after treatment (p<0.001) and there was a statistically significant difference in K-MBI and CDR-SB score changes than CR group (p<0.05). And chronic patient of IR group showed significant improvement in K-MBI, FIM, and CDR-SB after treatment (p<0.01) and there was a statistically significant difference in CDR-SB score changes than CR group (p<0.05). In particular, the earlier the treatment initiation time, the more the improvement in function and when the treatment started within 2 years from the onset and patients took acupuncture and pulsed electromagnetic therapy, all scales significantly improved (p<0.001). Conclusions IR showed more improvement on activities of daily life and cognitive functional recovery than CR in this study.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.1225-1228
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• 2004

We have studied the Polymer Stabilized Continuous Director Rotation (PSCDR) mode to solve the thermal shock problem which is core and main problem in CDR mode. The cell filled 95wt. % R2301 FLC and 5wt. % UCL-001 polymer is applied a low DC voltage only near the phase transition temperature from cholesteric to chiral smectic C phase transition to get defect-free alignment. In the previous work, we also confirmed layer deformation induced by an applied DC field only near the phase transition temperature from Ch to $SmC^{\ast}$. Results of layer structure, and characteristics of electro-optical properties between CDR and PSCDR mode will be discussed in this paper. We are also in progress to finalize the layer structures compared between CDR and PSCDR mode by x-ray measurements.

• Journal of information and communication convergence engineering
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• 제9권3호
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• pp.305-309
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• 2011

This paper proposes a new rotational frequency detector (RFD) for phase-locked loop (PLL) or clock and data recovery (CDR) applications for fast frequency acquisition. The proposed RFD uses the four states finite state machine (FSM) model to accelerate the frequency acquisition time. It is modeled and simulated with MATLAB Simulink. The functionalities of the proposed RFD are examined and the results are compared to those of a conventional RFD. The proposed RFD's frequency acquisition time is four times faster than that of a conventional one. The proposed RFD incorporated with a phase detector (PD) in PLL or CDR is expected to improve the frequency and phase acquisition performance later greatly.

• 전기전자학회논문지
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• 제14권1호
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• pp.40-46
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• 2010

This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using $0.18{\mu}m$ CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.287-292
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• 2016

A multiphase clock and data recovery (CDR) circuit having a novel rotational bang-bang phase detector (RBBPD) is demonstrated. The proposed 1/4-rate RBBPD decides the locking point using a single clock phase among sequentially rotating 4 clock phases. With this, our RBBPD has significantly reduced power consumption and chip area. A prototype 10-Gb/s 1/4-rate CDR with RBBPD is successfully realized in 65-nm CMOS technology. The CDR consumes 5.5 mW from 1-V supply and the clock signal recovered from $2^{31}-1$ PRBS input data has 0.011-UI rms jitter.

• Journal of Power Electronics
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• 제16권3호
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• pp.894-904
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• 2016

This study examines the zero-voltage switching (ZVS) operation of an active-clamped forward converter (ACFC) with a current-doubler rectifier (CDR). The ZVS condition can be obtained with a much smaller leakage inductance compared to that of a conventional ACFC. Due to the significantly reduced leakage inductance, the design is optimized and the circulating loss is reduced. The operation of the ACFC with a CDR is analyzed, and a detailed ZVS analysis is conducted on the basis of a steady-state analysis. From the results, a design consideration for ZVS improvement is presented. Loss analyses of the converters shows that enhanced soft-switching contributes to an efficiency improvement under light-load condition. Experimental results from a 100-W (5-V/20-A) prototype verify that the ACFC with a CDR can attain ZVS across an extended load range of loads and achieve a higher efficiency than conventional ACFCs.