• Journal of Korean Society for Quality Management
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• v.47 no.4
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• pp.725-737
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• 2019

Purpose: We used a data analysis method to improve semiconductor manufacturing yield. We defined and optimized important factors and applied our findings to a real-world process. The semiconductor industry is very cost-competitive; our findings are useful. Methods: We collected data on 15 independent variables and one dependent variable (yield); we removed outliers and missing values. Using SPSS Modeler ver. 18.0, we analyzed the data both continuously and discretely and identified common factors. Results: We optimized two independent variables in terms of process conditions; yield improved. We used DS Leak software to model netting and Contact CD software to model meshes. DS Leak shows smaller the better characterisrics and Contact CD shows normal the best characteristics Conclusion: Various efforts have been made to improve semiconductor manufacturing yields, and many studies have created models or analyzed various characteristics. We not only defined important factors but also showed how to control processing to improve semiconductor yield.

• Journal of the Semiconductor & Display Technology
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• v.9 no.4
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• pp.13-18
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• 2010

Extreme ultraviolet (EUV) lithography using 13.5 nm wavelengths is expected to be adopted as a mass production technology for 32 nm half pitch and below. One of the new issues introduced by EUV lithography is the shadowing effect. Mask shadowing is a unique phenomenon caused by using mirror-based mask with an oblique incident angle of light. This results in a horizontal-vertical (H-V) biasing effect and ellipticity in the contact hole pattern. To minimize the shadowing effect, a refilled mask is an available option. The concept of refilled mask structure can be implemented by partial etching into the multilayer and then refilling the trench with an absorber material. The simulations were carried out to confirm the possibility of application of refilled mask in 32 nm line-and-space pattern under the condition of preproduction tool. The effect of sidewall angle in refilled mask is evaluated on image contrast and critical dimension (CD) on the wafer. We also simulated the effect of refilled absorber thickness on aerial image, H-V CD bias, and overlapping process window. Finally, we concluded that the refilled absorber thickness for minimizing shadowing effect should be thinner than etched depth.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.107.1-107.1
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• 2014

We have developed and commercialize a time-of-flight - medium energy ion scattering spectrometry (TOF-MEIS) system (model MEIS-K120). MEIS-K120 adapted a large solid acceptance angle detector that results in high collection efficiency, minimized ion beam damage while maintaining a similar energy resolution. In addition, TOF analyzer regards neutrals same to ions which removes the ion neutralization problems in absolute quantitative analysis. A TOF-MEIS system achieves $7{\times}10^{-3}$ energy resolution by utilizing a pulsed ion beam with a pulse width 350 ps and a TOF delay-line-detector with a time resolution of about 85 ps. TOF-MEIS spectra were obtained using 100 keV $He^+$ ions with an ion beam diameter of $10{\mu}m$ with ion dose $1{\times}10^{16}$ in ordinary experimental condition. Among TOF-MEIS applications, we report the quantitative compositional profiling of 3~5 nm CdSe/ZnS QDs, As depth profile and substitutional As ratio of As implanted/annealed Si, Ionic Critical Dimension (CD) for FinFET, Direct Recoil (DR) analysis of hydrogen in diamond like carbon (DLC) and InxGayZnzOn on glass substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.100-105
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• 2004

The influencing factors on the OPC (optical proximity correction) results are quantitatively analyzed using OPCed L/S patterns. ${\sigma}$ values of proximity variations are measured to be 9.3 nm and 15.2 nm for PR-A and PR-B, respectively. The effect of post exposure bake condition is assessed. 16.2 nm and 13.8 nm of variations are observed. Proximity variations of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate the OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4, 13.9, and 15.2 nm are observed for the mask mean-to-targets of 0, 2 and 4 nm, respectively. The decrease the OPC grid size from 1 nm to 0.5 nm enhances the correction resolution and the OCV is reduced from 14.6 nm to 11.4 nm. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The critical dimension (CD) uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 9.9 nm and 8.7 nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved. The decrease of OPC grid size is shown to improve not only the proximity correction, but also the uniformity.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.316.2-316.2
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• 2016

Device가 점점 Shrinkage 됨에 따라 미세 패터닝을 위하여 기존에 사용하던 박막은 Hardmask 로써 CD(Critical Dimension)가 제한적으로 이를 개선하기 위한 비정질 실리콘 (amorphous silicon)으로 대체하여 사용되는 Layer의 수가 증가하고 있다. 하지만 비정질 실리콘을 증착 시, 하부막에 따른 Adhesion 및 Hillocks과 같은 공정상에서 발생하는 문제들이 발생하게 되는데, 이는 소자의 특성을 떨어뜨리게 된다. 이러한 문제를 해결하고자 본 연구에서는 PECVD를 사용하여 비정질 실리콘 박막을 증착하였고, 그 특성을 분석하였으며, Adhesion 및 Hillock 개선을 위해 비정질 실리콘 박막 증착 전 처리를 최적화하여 특성을 개선하였다. 증착된 박막의 두께 및 굴절률은 Auto thickness measurement로 분석하였고, 표면 특성은 Field emission scanning electron microscopy(FE-SEM 그림 참고), 4 Point Bending TEST를 이용하여 분석을 수행하였다.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.132-132
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• 2004

카본나노튜브는 나노튜브의 종류에 따라 1~10nm의 직경과 수 $\mu\textrm{m}$정도의 길이를 가지는 고종횡비(high aspect ratio)가 가능하며, 고강성, 전기화학적 내성, 마모에 대한 강인성 때문에 원자력간 현미경(AEM)의 프로브로서 이상적인 재료로 인식되어 왔다. 따라서 단백질이나 DNA를 측정하는 바이오 분야, 나노 일렉트로닉스 분야, 나노 구조 측정분야 등 나노 관련 측정분야에서 점차 그 활용도가 높아 져가고 있다. 특히 100nm이하의 반도체의 CD(critical Dimension)을 측정하는데 있어서 나노튜브는 가장 이상적인 후보라고 할 수 있겠다.(중략)

• Journal of the Korean Society for Precision Engineering
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• v.16 no.11
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• pp.98-105
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• 1999

As the IC(Integrated Circuit) has been densified and complicated, it is required to thorough process control to improve yield. Experts, for this purpose, focused on the process analysis automation, which is came from the strict data management in semiconductor manufacturing. In this paper, we presents the process analysis system that can analyze causes, for a output after processes. Also, the plasma etching process that highly affects yield among semiconductor process is modeled to predict a output before the process. To approach this problem, we use adaptively trained neural networks that exhibit superior accuracy over statistical techniques. And in comparison with methods in other paper, a method that history of trend for input data is considered is shown to offer advantage in both learning and prediction capability. This research regards CD(Critical Dimension) that is considerable in high integrated circuit as output variable of the prediction model.

• Korean Chemical Engineering Research
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• v.47 no.1
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• pp.79-83
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• 2009

In this study, the characteristics of amorphous silicon etching for the formation of gate electrodes have been evaluated at the variation of several process parameters. When total flow rates composed of $Cl_2/HBr/O_2$ gas mixtures increased, the etch rate of amorphous silicon layer increased, but critical dimension (CD) bias was not notably changed regardless of total flow rate. As the amount of HBr in the mixture gas became larger, amorphous silicon etch rate was reduced by the low reactivity of Br species. In the case of increasing oxygen flow rate, etch selectivity was increased due to the reduction of oxide etch rate, enhancing the stability of silicon gate etching process. However, gate electrodes became more sloped according to the increase of oxygen flow rate. Higher source power induced the increase of amorphous silicon etch rate and CD bias, and higher bias power had a tendency to increase the etch rate of amorphous silicon and oxide.

• Korean Journal of Optics and Photonics
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• v.9 no.3
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• pp.146-150
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• 1998

To enhance the resolution and the depth of focus of the patterns whose size reaches the optical resolution limits, the various imaging methods are being tried. Generally in the linear polarization illumination methods, the contrast gap exists between TE mode TM mode according to the pattern direction. However, through the previous research, the elliptical polarization illumination(EPI) method was proposed to overcome this contrast gap. In this research, we investigated the optimal polarization condition to be able to enhance the depth of focus(DOF) for the optional mask which is containing the opposite direction patterns by applying the various polarization conditions including EPI. The DOF according to each polarization condition was obtained by ED-Tree(Exposure-Defocus Tree) for the given exposure dose and CD error boundaries. As the result, we can ascertain th effect of EPI for the enhancement of DOF in some condition of optical system.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.