• The Journal of the Convergence on Culture Technology
• /
• v.6 no.2
• /
• pp.521-527
• /
• 2020

Quantum-dot cellular automata (QCA) is a technology that attracts attention as a next-generation digital circuit design technology, and several digital circuits have been proposed in the QCA environment. Content-addressable memory (CAM) is a storage device that conducts a search based on information stored therein and provides fast speed in a special process such as network switching. Existing CAM cell circuits proposed in the QCA environment have a disadvantage in that a required area and energy dissipation are large. The CAM cell is composed of a memory unit that stores information and a match unit that determines whether or not the search is successful, and this study proposes an improved QCA CAM cell by designing the memory unit in a multi-layer structure. The proposed circuit uses simulation to verify the operation and compares and analyzes with the existing circuit.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.6
• /
• pp.48-55
• /
• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4B
• /
• pp.604-612
• /
• 2000

In order to satisfy the desired QoS level associated with each existing connection, ATM networks require traffic policing during a connection. Users who respect the contract should receive the function of transparent traffic policing without any interruption. However, contract violations should be detected and mediated immediately. So we propose a CAM type policing controller to allow user cell streams to minimize additional delay. The proposed policing scheme controls policing actions including traffic shaping by suitably spacing cells on each virtual circuit. This policing action is based on parallel processing of multiple cell stream which arrive in ATM multiplexed virtual circuits. We have developed an analytical model of the proposed policing scheme to examine the amount of cell loss and delay, which depends on traffic load, the size of policing buffers and minimum spacing cell time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.2
• /
• pp.145-154
• /
• 1991

In this dissertation, the same reading and writing operation of general SRAM, the algonthm and hardware of 8 bit $\times$16 word CAM(Content Addressable Memory) which carry out the parallel that search is presented. The designed CAM chip consists of five functional blocks (CAM cell array, Address Deceden, Address Encoden. Data Selector, Sense Amplifier). The smulation is performed using logic smmulator on Apollo workstation and PSPICE eitcut simulation on PC/AT. The designed CAM was fabricated by 3um CMOS N Well process (ETRI) design nitles and testing was performed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.7B
• /
• pp.647-659
• /
• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.12
• /
• pp.1313-1323
• /
• 1991

n this thesis CAM(content Addressable Memory) generator and graphic display tool for run-plot sequence in automatic generation of CAM are presented. We show that implementing the layout generation, graphic menu, mouse driver, and data structure by using the basic classes is clear and easy in modification than the conventional procedural language. For the implementation of generator which is independent of design rule or process, we use the parameterized cell so that basic cell can be changed according to user's inputs. and perform the layout by means of placement and routing using pitch mathching. Finally, the display of CIF which generated and constitution of graphic menu for total run-plot sequence are explained.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.7
• /
• pp.1-9
• /
• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38C no.9
• /
• pp.781-786
• /
• 2013

Multiplexing information over parallel data channels based on RF MIMO concept is possible to achieve considerable data rates over large transmission ranges with just a single transmitting element. Visual multiplexing MIMO techniques will send independent streams of bits using the multiple elements of the light transmitter array and recording over a group of camera pixels can further enhance the data rates. The proposed system is a combination of the reliance on computer vision algorithms for tracking and OOK cell frame modulation. LED array are controlled to transmit message in the form of digital information using ON-OFF signaling with ON-OFF pulses (ON = bit 1, OFF = bit 0). A camera captures image frames of the array which are then individually processed and sequentially decoded to retrieve data. To demodulated data transmission, a motion tracking algorithm is implemented in OpenCV (Open source Computer Vision library) to classify the transmission pattern. One of the most advantages of proposed architecture is Computer Vision (CV) based image analysis techniques which can be used to spatially separate signals and remove interferences from ambient light. It will be the future challenges and opportunities for mobile communication networking research.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.10
• /
• pp.57-64
• /
• 2002

The structure of conventional CAM(Content Addressable Memory) cell, used to Look-up table scheme in Huffman CODEC, is not performed by being separated in reading, writing and match operation. So, there is disadvantages that the control is complicated, and the floating states of match line force wrong operation to be happened in reading, writing operation. In this paper, in order to improve the disadvantages and proces the data fast, fast Look-up table is designed using DBLCAM(Dual Bit Line CAM)-performing the reading, writing operation and match operation independently and Two-port SRAM being more fast than RAM in an access speed. Look-up table scheme in Huffman CODEC, using DBLCAM and Two-port SRAM proposed in this paper, is designed in Cadence tool, and layout is performed in 0.6${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS full custom. And simulation is peformed with Hspice.

• Geotechnical Engineering
• /
• v.11 no.3
• /
• pp.43-54
• /
• 1995

The aim of the work described in this paper is to develope a constitutive model for the prediction of an unsaturated soil and to confirm the application'of the model, which is composed of the elastic and plastic part in consideration of the matric suction and the net mean stress. From test results, volume changes and deviator stresses are analyzed at each state and their relationships are formulated. The application of the model to silty sands is confirmed by the comparison between test and predicted results. During drying -wetting and loading -unloading processes for isotropic states, the agreement between predicted and test results are satisfactory. Predicted deviator stresses are well agreed with test results in shearing process. Overall acceptable predictions are reproduced in high confining pressure. Usefulness of the model is confirmed for the unsaturated soil except volumetric strain, which is not well agreed with the test results due to deficiency of dilatancy of the model in low confining pressure. It is, therefore. recommended to study the behavior of dilatancy for an unsaturated soil.