• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.407-410
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• 2002

Thermal oxidations of 3C-SiC thin-films grown on Si(100) by APCVD(atmospheric pressure chemical vapor deposition) were carried out. The oxidations of 3C-SiC were performed at $1100^{\circ}C$ for 1~6 hr in wet and dry $O_2$ ambient, respectively. Ellipsometry was used to determine the thickness and index of refraction of oxide films. The oxide thickness vs. the oxidation time follows the general relationship used for the thermal oxidation of Si. The surface roughness was analyzed by using AFM(atomic force microscopy). The surface roughness of oxidized 3C-SiC was rougher than before oxidation. The thermal oxide was found to be $SiO_2$ by XPS(X-ray photoelectron spectroscopy) analysis. Auger analysis showed them to be homogeneous with near stoichiometric composition.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1526-1528
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• 2003

본 연구에서는 P-type Si wafer에 1000[$^{\circ}C$]의 조건에서 열산화방식으로 성장시킨 산화막($SiO_2$) 두께 3000[${\AA}$] 그 위에 APCVD방법으로 형성시킨 질화막($Si_3N_4$)의 두께 500[${\AA}$], 1500[${\AA}$]인 시료에 대하여 전기적 특징 중 유전정접 특성에 관하여 조사하였다. [1] 또한 각각의 두께에 대하여 측정 온도범위 상온${\sim}150[^{\circ}C]$ 와 인가전압 범위 1[V]${\sim}$20[V]에서 유전정접의 주파수 의존성과 온도 의존특성을 조사하고 특히 정전용량 변화에 따른 유전특성에 대하여 조사하고 변환기 소자재료 개발을 위한 기초물성을 실험한 결과를 보고한다.

• Current Photovoltaic Research
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• v.5 no.2
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• pp.59-62
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• 2017

Surface texturing is affected the uniformity and size of pyramid with saw mark defect density. To analysis the influence of the saw mark defect density, we textured various si wafer. When the texturing process proceeds without the saw mark removal, silicon wafer of low-saw mark defect density showed small pyramid size of $3.5{\mu}m$ with the lowest average value of the reflectance of 10.6%. When texturing carried out after removal of the saw mark using the TMAH solution, we obtained a reflectance of about 11% and the large pyramid size of $5{\mu}m$. As a result, saw mark wafers showed a better pyramid structure than saw mark-free wafer. This result showed that saw mark can take place more smooth etching by the KOH solution and saw mark-free wafer is determined to be a factor that have a higher reflectance and a large pyramid.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.207-207
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• 2006

We investigated the effects of hydrogen addition to the growth process of SiC single crystal using sublimation physical vapor transport(PVT) techniques. Hydrogen was periodically added to an inert gas for the growth ambient during the SiC bulk growth Grown 2"-SiC single crystals were proven to be the polytype of 6H-SiC and carrier concentration levels of about $10^{17}/cm^3$ was determined from Hall measurements. As compared to the characteristics of SiC crystal grown without using hydrogen addition, the SiC crystal without definitely exhibited lower carrier concentration and lower microplpe density as well as reduced growth rate.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.338-338
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• 2013

Monolithic three-dimensional integrated circuits (3D-ICs) 구현 시 bonding 과정에서 발생되는 aluminum (Al) 이나 copper (Cu) 등의 interconnect metal의 확산, 열적 스트레스, 결함의 발생, 도펀트 재분포와 같은 문제들을 피하기 위해서는 저온 공정이 필수적이다. 지금까지는 polymer 기반의 bonding이나 Cu/Cu와 같은 metal 기반의 bonding 등과 같은 저온 bonding 방법이 연구되어 왔다. 그러나 이와 같은 bonding 공정들은 공정 시 void와 같은 문제가 발생하거나 공정을 위한 특수한 장비가 필수적이다. 반면, 두 물질의 합금을 이용해 녹는점을 낮추는 eutectic bonding 공정은 저온에서 공정이 가능할 뿐만 아니라 void의 발생 없이 강한 bonding 강도를 얻을 수 있다. Aluminum-germanium (Al-Ge) 및 aluminum-indium (Al-In) 등의 조합이 eutectic bonding에 이용되어 각각 $424^{\circ}C$ 및 $454^{\circ}C$의 저온 공정을 성취하였으나 여전히 $400^{\circ}C$이상의 eutectic 온도로 인해 3D-ICs의 구현 시에는 적용이 불가능하다. 이러한 metal 조합들에 비해 indium (In)과 tin (Sn)은 각각 $156^{\circ}C$ 및 $232^{\circ}C$로 굉장히 낮은 녹는점을 가지고 있기 때문에 In-Sn 조합은 약 $120^{\circ}C$ 정도의 상당히 낮은eutectic 온도를 갖는다. 따라서 본 연구팀은 In-Sn 조합을 이용하여 $200^{\circ}C$ 이하에서monolithic 3D-IC 구현 시 사용될 eutectic bonding 공정을 개발하였다. 100 nm SiO2가 증착된 Si wafer 위에 50 nm Ti 및 410 nm In을 증착하고, 다른Si wafer 위에 50 nm Ti 및 500 nm Sn을 증착하였다. Ti는 adhesion 향상 및 diffusion barrier 역할을 위해 증착되었다. In과 Sn의 두께는 binary phase diagram을 통해 In-Sn의 eutectic 온도인 $120^{\circ}C$ 지점의 조성 비율인 48 at% Sn과 52 at% In에 해당되는 410 nm (In) 그리고 500 nm (Sn)로 결정되었다. Bonding은 Tbon-100 장비를 이용하여 $140^{\circ}C$, $170^{\circ}C$ 그리고 $200^{\circ}C$에서 2,000 N의 압력으로 진행되었으며 각각의 샘플들은 scanning electron microscope (SEM)을 통해 확인된 후, 접합 강도 테스트를 진행하였다. 추가로 bonding 층의 In 및 Sn 분포를 확인하기 위하여 Si wafer 위에 Ti/In/Sn/Ti를 차례로 증착시킨 뒤 bonding 조건과 같은 온도에서 열처리하고secondary ion mass spectrometry (SIMS) profile 분석을 시행하였다. 결론적으로 본 연구를 통하여 충분히 높은 접합 강도를 갖는 In-Sn eutectic bonding 공정을 $140^{\circ}C$의 낮은 공정온도에서 성공적으로 개발하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.429-429
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• 2012

To investigate the gettering effect of B-doped n-type monocrystalline silicon wafer, we made the p-n junction by diffusing boron into n-type monocrystalline Si substrate and then oxidized the boron doped n-type monocrystalline silicon wafer by in-situ wet and dry oxidation. After oxidation, the minority carrier lifetime was measured by using microwave photoconductance and the sheet resistance by 4-point probe, respectively. The junction depth was analyzed by Secondary Ion Mass Spectrometry (SIMS). Boron diffusion reduced the metal impurities in the bulk of silicon wafer and increased the minority carrier lifetime. In the case of wet oxidation, the sheet resistance value of ${\sim}46{\Omega}/{\Box}$ was obtained at $900^{\circ}C$, depostion time 50 min, and drive-in time 10 min. Uniformity was ~7% at $925^{\circ}C$, deposition time 30 min, and drive-in time 10 min. Finally, the minority carrier lifetime was shown to be increased from $3.3{\mu}s$ for bare wafer to $21.6{\mu}s$ for $900^{\circ}C$, deposition 40 min, and drive-in 10 min condition. In the case of dry oxidation, for the condition of 50 min deposition, 10 min drive-in, and O2 flow of 2000 SCCM, the minority carrier lifetime of 16.3us, the sheet resistance of ${\sim}48{\Omega}/{\Box}$, and uniformity of 2% were measured.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.322-322
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• 2010

For boron doping on n-type silicon wafer, around $1,000^{\circ}C$ doping temperature is required, because of the relatively low solubility of boron in a crystalline silicon comparing to the phosphorus case. Boron doping by fiber laser annealing and lamp furnace heat treatment were carried out for the uniformly deposited p-a-Si:H layer. Since the uniformly deposited p-a-Si:H layer by cluster is highly needed to be doped with high temperature heat treatment. Amorphous silicon layer absorption range for fiber laser did not match well to be directly annealed. To improve the annealing effect, we introduce additional lamp furnace heat treatment. For p-a-Si:H layer with the ratio of $SiH_4:B_2H_6:H_2$=30:30:120, at $200^{\circ}C$, 50 W power, 0.2 Torr for 30 min. $20\;mm\;{\times}\;20\;mm$ size fiber laser cut wafers were activated by Q-switched fiber laser (1,064 nm) with different sets of power levels and periods, and for the lamp furnace annealing, $980^{\circ}C$ for 30 min heat treatment were implemented. To make the sheet resistance expectable and uniform as important processes for the $p^+$ layer on a polished n-type silicon wafer of (100) plane, the Q-switched fiber laser used. In consequence of comparing the results of lifetime measurement and sheet resistance relation, the fiber laser treatment showed the trade-offs between the lifetime and the sheet resistance as $100\;{\omega}/sq.$ and $11.8\;{\mu}s$ vs. $17\;{\omega}/sq.$ and $8.2\;{\mu}s$. Diode level device was made to confirm the electrical properties of these experimental results by measuring C-V(-F), I-V(-T) characteristics. Uniform and expectable boron heavy doped layers by fiber laser and lamp furnace are not only basic and essential conditions for the n-type crystalline silicon solar cell fabrication processes, but also the controllable doping concentration and depth can be established according to the deposition conditions of layers.

• Journal of the Korean institute of surface engineering
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• v.40 no.6
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• pp.279-282
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• 2007

Cr-Mo-Si-C-N coatings were deposited on steel and Si wafer by a hybrid system of AIP and sputtering techniques using Cr, Mo and Si target in $Ar/N_2/CH_4$ gaseous mixture. Instrumental analyses of XRD and XPS revealed that the Cr-Mo-Si-C-N coatings must be a composite consisting of fine(Cr, Mo and Si)(C and N) crystallites and amorphous $Si_3N_4$ and SiC. The hardness value of Cr-Mo-Si-C-N coatings significantly increased from 41 GPa of Cr-Mo-C-N coatings to about 53 GPa with Si content of 9.3 at.% due to the refinement of (Cr, Mo and Si)(C and N) crystallites and the composite microstructure characteristics. A systematic investigation of the microstructures and mechanical properties of Cr-Mo-Si-C-N coatings prepared with various Si contents is reported in this paper.

• Electrical & Electronic Materials
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• v.10 no.1
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• pp.8-14
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• 1997

The UV/O$_{3}$ dry cleaning has been well known in removing organic molecules. The UV/O$_{3}$ dry cleaning method was performed to clean the Si wafer surfaces and contact holes contaminated by organic molecules such as residual PR. During the cleaning process, the Si surfaces were analyzed with X-ray photoelectron spectroscopy (XPS), atomic force microscope (AFM) and ellipsometer. When the UV/O$_{3}$ dry cleaning at 200'C was performed for 3 minutes, the residual photoresist was almost removed on Si wafer surfaces, but Si surfaces were oxidized. For UV/O$_{3}$ application of contact hole cleaning, the contact string were formed using the equipment of ISRC (Inter-university Semiconductor Research Center). Before Al deposition, UV/O$_{3}$ (at 200.deg. C) dry cleaning was performed for 3 minutes. After metal annealing, the specific contact resistivity was measured. Because UV/O$_{3}$ dry cleaning removed organic contaminants in contact holes, the specific contact resistivity decreased. Each contact hole size was different, but the specific contact resistivities were all much the same. Thus, it is expected that the UV/O$_{3}$ dry cleaning method will be useful method of removal of the organic contaminants at smaller contact hole cleaning.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.10
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• pp.817-821
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• 2000

In this work, we have investigated the dependence of annealing temperature(T$\_$a/) on optical and electrical properties of amorphous hydrogenated SiC(a-SiC:H) films. The a-SiC:H films were deposited on corning glass and p-type Si(100) wafer by PECVD (plasma enhanced vapor deposition) using SiH$_4$+CH$_4$+N$_2$ gas mixture. The experimental results have shown that the optical energy band gap(E$\_$opt/)of the thin films annealed at high temperatures have shown that the graphitization of carbon clusters and micro-crystalline silicon occurs. The current-voltage characteristics have shown good electrical properties at the annealed films.