• Journal of IKEEE
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• v.22 no.4
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• pp.1226-1229
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• 2018

We investigated the improvement of surface roughness and states after high temperature annealing using reduced-graphene oxide (r-GO) capping layer on ion-implanted 4H-SiC epitaxial layer. The specification of the 4H-SiC wafer grown on n-type $4^{\circ}$ off-axis 4H-SiC was $10{\mu}m$-thick and n-type epitaxial layer with a dose of $1.73{\times}10^{15}cm^{-2}$. The $n^+$ region were formed by multiple nitrogen ion-implantations and r-GO capping layer was produced by spray coating method. AFM measurements revealed that RMS value of the sample capped with r-GO was tenfold decrease compared to the sample without r-GO capping. The improvement of surface states was also verified by the improvement of leakage current level.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.25 no.2
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• pp.51-55
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• 2015

The present research is focused on the effect of porous graphite what is influenced on the 4H-SiC crystal growth by PVT method. We expect that it produces more C-rich and a change of temperature gradient for polytype stability of 4H-SiC crystal as adding the porous graphite in the growth cell. The SiC seeds and high purity SiC source materials were placed on opposite side in a sealed graphite crucible which was surrounded by graphite insulator. The growth temperature was around $2100{\sim}2300^{\circ}C$ and the growth pressure was 10~30 Torr of an argon pressure with 5~15 % nitrogen. 2 inch $4^{\circ}$ off-axis 4H-SiC with C-face (000-1) was used as a seed material. The porous graphite plate was inserted on SiC powder source to produce a more C-rich for polytype stability of 4H-SiC crystal and uniform radial temperature gradient. While in case of the conventional crucible, various polytypes such as 6H-, 15R-SiC were observed on SiC wafers, only 4H-SiC polytype was observed on SiC wafers prepared in porous graphite inserted crucible. The defect level such as MP and EP density of SiC crystal grown in the conventional crucible was observed to be higher than that of porous graphite inserted crucible. The better crystal quality of SiC grown using porous graphite plate was also confirmed by rocking curve measurement and Raman spectra analysis.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.76-84
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• 1994

The characteristics of 3 inch wafer scale GaAs epitaxial wafer grown by molecular beam epitaxy for LSI process application were studied. The thickness and doping uniformity are characterized and discussed. The growth temperature and growth rate were $600^{\circ}C$ by pyrometer, and 1 $\mu$m/h, respectively. It was found that thickness and doping uniformity were 3.97% and 4.74% respectively across the full 3 inch diameter GaAs epitaxial layer. Also, ungated MESFETs have been fabricated and saturation current measurement showed 4.5% uniformity on 3 inch, epitaxial layer, but uniformity of threshold voltage increase up to 9.2% after recess process for MESFET device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.6
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• pp.512-518
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• 2006

In this paper, we investigated the deposition of pentacene thin film on a large area substrate by Organic Vapor Phase Deposition(OVPD) and applied it to fabrication of Organic Thin Film Transistor(OTFT). We extracted the optimum deposition conditions such as evaporation temperature of $260^{\circ}C$, carrier gas flow rate of 10 sccm and chamber vacuum pressure of 0.1 torr. We fabricated 72 OTFTs on the 4 inch size Si Wafer, Which produced the average mobility of $0.1{\pm}0.021cm^2/V{\cdot}s$, average subthreshold slope of 1.04 dec/V, average threshold voltage of -6.55 V, and off-state current is $0.973pA/{\mu}m$. The overall performance of pentacene TFTs over 4 ' wafer exhibited the uniformity with the variation less than 20 %. This proves that OVPD is a suitable methode for the deposition of organic thin film over a large area substrate.

• Journal of Sensor Science and Technology
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• v.24 no.1
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• Journal of the Korean Vacuum Society
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• v.4 no.S2
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• pp.115-130
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• 1995

In order to produce Cu nanocrystallite in silicon wafer, the implantation technique was used. The samples of silicon (100) wafers were implanted by $Cu^+$ ions at 100 keV and with varying the doses at room temperature. Post-annealing was performed at $800^{\circ}C$ with Ar environment. To investigate the formation of Cu nanocrystallite with ion doses and growth process by thermal annealing, SIMS and HRTEM(high resolution transmission electron microscopy)spectra were studied.

• Journal of the Korean Ceramic Society
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• v.30 no.9
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• pp.695-700
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• 1993

In this study, we prepared Pb-Ti stock solution by sol-gel processing and deposited PbTiO3 thin film on a Pt coated SiO2/Si wafer by spin coating using the stock solution. We used lead acetate trihydrate and titanium isopropoxide. The stock solution was partially hydrolized and finally a 0.25M coating solution was prepared. We achieved spin coating at 4000rpm for 30 seconds and heated the thin film at 375$^{\circ}C$ for 5 minutes and at $600^{\circ}C$ for 5 minutes successively, first and second heating state. And the thin film was finally sintered at 90$0^{\circ}C$ for 1 hour in the air. The upper electrode of the thin film was made by gold sputtering and was cricle shape with radius 0.4mm. Measured dielectric constant, dissipation factor and phase transition temperature(Cuire Temp.) were about 275, 0.02 and 521$^{\circ}C$ respectively. To observe ferroelectric characteristics we calculated Pr(remnant polarization) and Ec(coercive field) byhysteresis curve. Ec was 72kV/cm and Pr was 11.46$\mu$C/$\textrm{cm}^2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.277-277
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• 2013

The epitaxial graphene on the 4H- or 6H-SiC(0001) surface has been intensively studied due to the possibility of wafer-scale growt. However the existence of interface layer (zero layer graphene) and its influence on the upper graphene layer have been considered as one of the main obstarcles for the industrial application. Among various methods tried to overcome the strong interaction with the substrate through the interface layer, it has been proved that the hydrogen intercalation successfully passivate the Si dangling bond of the substrate and can produce the quasi-free standing epitaxial graphene (QFEG) layers on the siC(0001) surface. In this study, we report the results of the angle-resolved photoemission spectroscopy (ARPES) and Raman spectroscopy for the QFEG layers produced by ex-situ and in-situ hydrogen intercalation.From the ARPES measurement, we confirmed that the Dirac points of QFEG layers exactly coincide with the Fermi level. The band structure of QFEG layer are sustainable upon thermal heating up to 1100 K and robust against the deposition of several metals andmolecular deposition. We also investigated the strain of the QFEG layers by using Raman spectroscopy measurement. From the change of the 2D peak position of graphene Raman spectrum, we found out that unlike the strong compressive strain in the normal epitaxial graphene on the SiC(0001) surface, the strain of the QFEG layer are significantly released and almost similar to that of the mechanically exfoliated graphene on the silicon oxide substrate. These results indicated that various ideas proposed for the ideal free-standing graphene can be tested based on the QFEG graphene layers grown on the SiC(0001) surface.

• Journal of the Korean Ceramic Society
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• v.31 no.7
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• pp.795-803
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• 1994

Ferroelectric BaTiO3 thin film was produced using BaTi-ethoxide sol. This sol was prepared from BaTi-ethoxide by a partial hydrolysis with ammonia as a basic catalyst and ethylene glycol as a chelating agent. BaTiO3 thin film was prepared from three continuous spin-coating layers of the sol on bare Si(100) wafer at 2500 rpm followed by pyrolysis at $700^{\circ}C$ for 30 min. After the heat treatment, the film was 0.200$\pm$0.010 ${\mu}{\textrm}{m}$ thick and its grain size was 0.059 ${\mu}{\textrm}{m}$. On the other hand, electrical properties were measured for BaTiO3 thin film separately prepared on Au-deposited silicon wafer. The dielectric constant and loss of the BaTiO3 thin film at room temperature was 150~160 and 0.04 respectively, which was measured at 10 kHz and oscillation level of 0.1 V. In the measurements of the dielectric properties at high temperatures, it was observed that the capacitance of the thin film increases steeply, while the dielectric loss reaches maximum around 1$25^{\circ}C$, which corresponds a phase transition from tetragonal to cubic BaTiO3.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.