• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.3
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• pp.205-210
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• 2000

Lead titanate thin films were fabricated on Si(100) wafer and ITO-coated glass substrates by metal organic chemical vapor deposition using ultrasonic spraying. When the ratio (Ti/Pb) of starting materials was 1.2, the films deposited on Si wafer had a single perovskite phase. The films deposited on ITO-coated glass had higher growth rate than that on Si wafer. As deposition temperature was increased from $530^{\circ}C$ to $570^{\circ}C$, dielectric constant was increased due to the increase of crystallinity and grain size. At $570^{\circ}C$, dielectric constant and dielectric loss of the films were 205 and 0.016, respectively. When the deposition temperature is higher than $600^{\circ}C$, dielectric constant was decreased.

• Journal of the Korean Ceramic Society
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• v.48 no.4
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• pp.312-315
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• 2011

The effect of slurry composition and wafer flatness on a material removal rate (MRR) and resulting surface roughness which are evaluation parameters to determine the CMP characteristics of the on-axis 6H-SiC substrate were systematically investigated. 2-inch SiC wafers were fabricated from the ingot grown by a conventional physical vapor transport (PVT) method were used for this study. The SiC substrate after the CMP process using slurry added oxidizers into slurry consisted of KOH-based colloidal silica and nano-size diamond particle exhibited the significant MRR value and a fine surface without any surface damages. SiC wafers with high bow value after the CMP process exhibited large variation in surface roughness value compared to wafer with low bow value. The CMPprocessed SiC wafer having a low bow value of 1im was observed to result in the Root-mean-square height (RMS) value of 2.747 A and the mean height (Ra) value of 2.147 A.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.23-28
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• 2009

We investigated the wafer-level MEMS capping process for which cavity formation in Si wafer was not required. Ni caps were formed by electrodeposition on 4" Si wafer and Ni rims of the Ni caps were bonded to the Cu rims of bottom Si wafer by using epoxy. Then, top Si wafer was debonded from the Ni cap structures by using SnBi layer of low melting temperature. As-evaporated SnBi layer was composed of double layers of Bi and Sn due to the large difference in vapor pressures of Bi and Sn. With keeping the as-evaporated SnBi layer at $150^{\circ}C$ for more than 15 sec, SnBi alloy composed of eutectic phase and Bi-rich $\beta$ phase was formed by interdiffusion of Sn and Bi. Debonding between top Si wafer and Ni cap structures was accomplished by melting of the SnBi layer at $150^{\circ}C$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.6
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• pp.479-485
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• 2002

We have investigated the effects of various wafers cleaning on glass/Si bonding using 4 inch Pyrex glass wafers and 4 inch silicon wafers. The various wafer cleaning methods were examined; SPM(sulfuric-peroxide mixture, $H_2SO_4:H_2O_2$ = 4 : 1, $120^{\circ}C$), RCA(company name, $NH_4OH:H_2O_2:H_2O$ = 1 : 1 : 5, $80^{\circ}C$), and combinations of those. The best room temperature bonding result was achieved when wafers were cleaned by SPM followed by RCA cleaning. The minimum increase in surface roughness measured by AFM(atomic force microscope) confirmed such results. During successive heat treatments, the bonding strength was improved with increased annealing temperatures up to $400^{\circ}C$, but debonding was observed at $450^{\circ}C$. The difference in thermal expansion coefficients between glass and Si wafer led debonding. When annealed at fixed temperatures(300 and $400^{\circ}C$), bonding strength was enhanced until 28 hours, but then decreased for further anneal. To find the cause of decrease in bonding strength in excessively long annealing time, the ion distribution at Si surface was investigated using SIMS(secondary ion mass spectrometry). tons such as sodium, which had been existed only in glass before annealing, were found at Si surface for long annealed samples. Decrease in bonding strength can be caused by the diffused sodium ions to pass the glass/si interface. Therefore, maximum bonding strength can be achieved when the cleaning procedure and the ion concentrations at interface are optimized in glass/Si wafer direct bonding.

• Journal of Sensor Science and Technology
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• v.1 no.2
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• pp.131-145
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• 1992

This paper has been described a process technology for the fabrication of Si-on-insulator(SOI) transducers and circuits. The technology utilizes Si-wafer direct bonding(SDB) and mechanical-chemical(M-C) local polishing to create a SOI structure with a high-qualify, uniformly thin layer of single-crystal Si. The electrical and piezoresistive properties of the resultant thin SOI films have been investigated by SOI MOSFET's and cantilever beams, and confirmed comparable to those of bulk Si. Two kinds of pressure transducers using a SOI structure have been proposed. The shifts in sensitivity and offset voltage of the implemented pressure transducers using interfacial $SiO_{2}$ films as the dielectrical isolation layer of piezoresistors were less than -0.2% and +0.15%, respectively, in the temperature range from $-20^{\circ}C$ to $+350^{\circ}C$. In the case of pressure transducers using interfacial $SiO_{2}$ films as an etch-stop layer during the fabrication of thin Si membranes, the pressure sensitivity variation can be controlled to within a standard deviation of ${\pm}2.3%$ from wafer to wafer. From these results, the developed SDB process and the resultant SOI films will offer significant advantages in the fabrication of integrated microtransducers and circuits.

• New & Renewable Energy
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• v.4 no.2
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• pp.68-73
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• 2008

It is very important that constitution of good hetero-junction interface with a high quality amorphous silicon thin films on very cleaned c-Si wafer for making high efficiency hetero-junction solar cells. For achieving the high efficiency solar cells, the inspection and management of c-Si wafer surface conditions are essential subjects. In this experiment, we analyzed the c-Si wafer surface very sensitively using Spectroscopic Ellipsometer for < ${\varepsilon}2$ > and u-PCD for effective carrier life time, so we accomplished < ${\varepsilon}2$ > value 43.02 at 4.25eV by optimizing the cleaning process which is representative of c-Si wafer surface conditions very well. We carried out that the deposition of high quality hydrogenated silicon amorphous thin films by RF-PECVD systems having high density and low crystallinity which are results of effective medium approximation modeling and fitting using spectroscopic ellipsometer. We reached the cell efficiency 12.67% and 14.30% on flat and textured CZ c-Si wafer each under AM1.5G irradiation, adopting the optimized cleaning and deposition conditions that we made. As a result, we confirmed that spectroscopic ellipsometry is very useful analyzing methode for hetero-junction solar cells which need to very thin and high quality multi layer structure.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.2020-2022
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS fileds because of its application possibility in harsh environements. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The PECVD oxide was characterized by XPS and AFM, respectively. The characteristics of bonded sample were measured under different bonding conditions of HF concentration and applied pressure, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$cm^2{\sim}$ Max : 15.5 kgf/$cm^2$).

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.8 no.2
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• pp.233-239
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• 1998

SiC thin films were deposited by chemical vapor deposition method using tetramethylsilane (TMS) and hexamethyldisilane (HMDS). The chamber pressure during the deposition was kept at about 1 torr. Precursor was transported to the reaction chamber by $H_2$gas and SiC deposition was carried out at the reaction temperature of $1200^{\circ}C$. Si-wafer masked with tantalum and MgO single crystal covered with platinum and molybdenum were used as substrates. The selectivity of SiC deposition was observed by comparing the microstructure between metal (Ta, Pt, and Mo) surfaces and substrate surfaces (Si and MgO). The deposited films were identified as the $\beta-SiC$ phase by X-ray diffraction pattern. Also, the deposition -behavior of SiC on each surface was investigated by the scanning electron microscope analysis.

• Korean Journal of Materials Research
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• v.12 no.2
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• pp.117-120
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• 2002

We investigated the possibility of direct bonding of the Si ∥SiO$_2$/Si$_3$N$_4$∥Si wafers for Oxide-Nitride-Oxide(ONO) gate oxide applications. 10cm-diameter 2000$\AA$-thick thermal oxide/Si(100) and 500$\AA$-Si$_3$N$_4$LPCVD/Si (100) wafers were prepared, and wet cleaned to activate the surface as hydrophilic and hydrophobic states, respectively. Cleaned wafers were premated wish facing the mirror planes by a specially designed aligner in class-100 clean room immediately. Premated wafer pairs were annealed by an electric furnace at the temperatures of 400, 600, 800, 1000, and 120$0^{\circ}C$ for 2hours, respectively. Direct bonded wafer pairs were characterized the bond area with a infrared(IR) analyzer, and measured the bonding interface energy by a razor blade crack opening method. We confirmed that the bond interface energy became 2,344mJ/$\m^2$ when annealing temperature reached 100$0^{\circ}C$, which were comparable with the interface energy of homeogenous wafer pairs of Si/Si.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.7 no.2
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• pp.191-196
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• 1997

The micro-defects in the SiC single crystals were characterized using a variety of the microscopic techniques (OM, TEM, AFM). It was observed that the hexagonal-plate precipitates and the longitudinal micropipes are present inside of SiC wafers. TEM results exhibited that there are amorphous phase in the SiC wafer and the phase were originated from the formation of the nonstoichiometric $Si_{1-x}_xC_x$ phases during growth process.