• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• Proceedings of the KWS Conference
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• 2007.11a
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• pp.235-237
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• 2007

In this paper, fabrication of Sn-3.0Ag-0.5Cu solder bumping having accurate composition and behavior of intermetallic compounds(IMCs) growth at interface between Sn-Ag-Cu bumps and Cu substrate were studied. The ternary alloy of the Sn-3.0Ag-0.5Cu solder was made by two binary(Sn-Cu, Sn-Ag) electroplating on Cu pad. For the manufacturing of the micro-bumps, photo-lithography and reflow process were carried out. After reflow process, the micro-bumps were aged at $150^{\circ}C$ during 1 hr to 500 hrs to observe behavior of IMCs growth at interface. As a different of Cu contents(0.5 or 2wt%) at Sn-Cu layer, behavior of IMCs was estimated. The interface were observed by FE-SEM and TEM for estimating of their each IMCs volume ratio and crystallographic-structure, respectively. From the results, it was found that the thickness of $Cu_3Sn$ layer formed at Sn-2.0Cu was thinner than the thickness of that layer be formed Sn-0.5Cu. After aging treatment $Cu_3Sn$ was formed at Sn-0.5Cu layer far thinner.

• Journal of Acupuncture Research
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• v.30 no.1
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• pp.43-55
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• 2013

I investigated whether snake venom toxin(SVT) from Vipera lebetina turanica enhances the apoptosis ability of tumor necrosis factor(TNF)-related apoptosis-inducing ligand(TRAIL) in cancer cells. TRAIL inhibited HCT116 cell growth in a dose-dependent manner. Consistent with cell growth inhibition, the expression of TRAIL receptors; DR4 and DR5 was significantly increased as well as apoptosis related proteins such as cleaved caspase-3, 8, 9 and Bax. However, the expression of survival proteins(eg, cFLIP, survivin, XIAP and Bcl2) was suppressed by the combination treatment of SVT and TRAIL. Pretreatment with the reactive oxygen species(ROS) scavenger N-acetylcysteine reduced the SVT and TRAIL-induced upregulation of DR4 and DR5 expression and expression of the apoptosis related protein such as caspase-3 and-9 as well as cell growth inhibitory effects. The collective results suggest that SVT facilitates TRAIL-induced apoptosis in human colorectal cancer HCT116 cells through up-regulation of the TRAIL receptors; DR4 and DR5 via ROS pathway signals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.140-148
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• 2008

Using the self duality of an optimal normal basis(ONB) of type II, we present a bit parallel and bit serial systolic arrays over GF($2^m$) which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches(flip-flops). Comparing with other arrays of the same kinds, we find that our array has significantly reduced latency and hardware complexity.

• Journal of the Korean Magnetic Resonance Society
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• v.26 no.4
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• pp.51-58
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• 2022

The baseline flattened NMR spectrum has been achieved by several methodologies including pulse manipulation with a series of phase cycling. The background signal inherent in the probe is also main source of baseline distortion both in solution and solid NMR. The simple direct polarization with 90° pulse flipping the magnetization from the z-axis onto the receiver coil requires the strong rf pulse enough to encompass the wide frequency range to excite the resonance of interest nuclei. Albeit the perfect polarization 90° pulse, the signal from the unwanted magnetic fields such as background signal can not be completely suppressed by suitable phase cycling. Moreover, slowly baseline wiggling signal from the low 𝛾 nuclei is not easy to eliminate with multiple pulse manipulation. So there is still need to contrive the new scheme for that purpose in an adroit manner. In this article new triple pulse excitation schemes for TIP and modified DEPTH pulse sequence are analytically examined in terms of arbitrary phase and flip angle of pulse. The suitable phase cycling for these pulse trains is necessary for the good sensitivity and resolution of the spectrum. It is observed that the ¹³C sensitivity TIP experiment is almost equal to the CP/MAS with modified DEPTH sequence, both of which are applicable to both solid and solution state NMR.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.246-251
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• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.73-82
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• 2005

Test data volume and power consumption for scan vectors are two major problems in system-on-a-chip testing. Therefore, this paper proposes a new test data compression/decompression method for low power testing. The method is based on analyzing the factors that influence test parameters: compression ratio, power reduction and hardware overhead. To improve the compression ratio and the power reduction ratio, the proposed method is based on Modified Statistical Coding (MSC), Input Reduction (IR) scheme and the algorithms of reordering scan flip-flops and reordering test pattern sequence in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data, not $T_{diff}$, and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead and lower power consumption than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Korean Journal of Optics and Photonics
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• v.10 no.6
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• pp.500-506
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• 1999

We designed and fabricated a bidirectional optical transceiver module for low cost access network. An integrated chip forming a pin-PD on an 1.3 urn FP-LD was assembled by flip-chip bonding on a Si optical bench, a single mode fiber with an angled end facet was aligned passively with the integrated chip on V-groove of Si-optical bench. Gaussian beam theory was applied to evaluate the coupling coefficients as a function of some parameters such as alignment distance, angle of fiber end facet, vertical alignment error. The theory is also used to search the bottle-neck between transmittance and receiving coupling efficiency in the bi-directional optical system. Tn this paper, we confirmed that reduction of coupling efficiency by the vertical alignment error between laser beam and fiber core axis can be compensated by controlling the fiber facet angle. In the fabrication of sub-module, a'||'&'||' we made such that the fiber facet have a corn shape with an angled facet only core part, the reflection of transmitted laser beam from the fiber facet could be minimized below -35 dE in alignment distance of 2: 30 /J.m. In the same condition, transmitted output power of -12.1 dEm and responsivity of 0.2. AIW were obtained.

• Journal of the Korean Vacuum Society
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• v.16 no.4
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• pp.262-266
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• 2007

Polycrystalline $Mn_xFe_{3-x}O_4$ thin films were synthesized on Si(100) substrates using sol-gel method and the effects of Mn substitution on the structural, magnetic, and magnetotransport properties were analyzed. X-ray diffraction revealed that cubic structure is maintained up to x = 1.78 with increasing lattice constant for increasing x. Such increase of the lattice constant is attributable to the substitution of $Mn^{2+}$ (with larger ionic radius) ions into tetrahedral $Fe^{3+}$(with smaller ionic radius) sites. VSM measurements revealed that $M_s$ does not vary significantly with x, qualitatively explainable by comparing spin magnetic moments of Mn and Fe ions. On the other hand, $H_c$ was found to decrease with increasing x, attributable to the decrease of magnetic anisotropy due to the decrease of $Fe^{2+}$ density through $Mn^{2+}$ substitution. Magnetoresistance (MR) of the $Mn_xFe_{3-x}O_4$ films was found to decrease with increasing x. Analysis of the MR data in comparison with the VSM results gives an indication of the tunneling of spin-polarized carriers through the grain boundaries of the polycrystalline samples at low external field and spin-flip of the carriers at high external field.