• 조명전기설비학회논문지
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• 제29권8호
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• pp.18-22
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• 2015

Digitalization of the substation in Korea has been in progress so far with focusing on Station Bus. However, its application to Process Bus has been delayed due to some technical issues. IEDs based on Process Bus use the data values of SV and GOOSE. As the size of communication data on Process Bus is comparatively bigger than that of Station Bus, it is very important for the evaluating the performance of Process Bus to analyze the transferring speed and quality of data from the first equipment, which is located on process level, to station level. According to the results of related studies, it is said that the most important factor for the design and operation of Process Bus network is the communication delay with consideration of the volume of packets. In the paper, the results of performance test for the network with and without application of VLAN on Process Bus system that uses integrated IEDs are presented. Additionally, the paper proposes the optimal method to analyze the communication delays of network systems through evaluating the maximum delay time, link process ratio and the amount of lost packets by using a simulation tool.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 B
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• pp.643-645
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• 1996

In order to improve the voltage profile of the system we introduce the reactive power devices. However, it is difficult to know which bus will be the most effective bus when we inject the reactive power supplier in it. This paper systematically determines indices of the system in order to locate reactive power devices in a power system. To prove the validity and effectiveness of the system we apply the proposed method to the 9 bus system.

• Journal of Electrical Engineering and Technology
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• 제10권2호
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• pp.474-486
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• 2015

This paper proposes a multi-objective optimal placement method of Phasor Measurement Units (PMUs) in large electric transmission systems. It is proposed for minimizing the number of PMUs for complete system observability and maximizing measurement redundancy of the buses, simultaneously. The measurement redundancy of the bus indicates that number of times a bus is able to monitor more than once by PMUs set. A high level of measurement redundancy can maximize the system observability and it is required for a reliable power system state estimation. Therefore, simultaneous optimizations of the two conflicting objectives are performed using a binary coded firefly algorithm. The complete observability of the power system is first prepared and then, single line loss contingency condition is added to the main model. The practical measurement limitation of PMUs is also considered. The efficiency of the proposed method is validated on IEEE 14, 30, 57 and 118 bus test systems and a real and large- scale Polish 2383 bus system. The valuable approach of firefly algorithm is demonstrated in finding the optimal number of PMUs and their locations by comparing its performance with earlier works.

• 대한전기학회논문지:전력기술부문A
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• 제53권10호
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• pp.565-572
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• 2004

This paper proposes an expert system which can enhance the accuracy of real-time bus reconfiguration strategy by adopting local minimum tree search method and minimize the spreading effect of the fault by considering totally the operating condition when a main transformer fault occurs in the automated substation. The local minimum tree search method to expand the best-first search method. This method has an advantage which can improve the performance of solution within the limits of the real-time condition. The inference strategy proposed expert system consists of two stages. The first stage determines the switching candidate set by searching possible switching candidates starting from the main transformer or busbar related to the event. And, second stage determines the rational real-time bus reconfiguration strategy based on heuristic rules for the obtained switching candidate set. Also, this paper studies the generalized distribution substation modelling using graph theory and a substation database is designed based on the study result. The inference engine of the expert system and the substation database is implemented in MFC function of Visual C++. Finally, the performance and effectiveness of the proposed expert system is verified by comparing the best-first search solution and local minimum tree search solution based on diversity event simulations for typical distribution substation.

• 한국지능시스템학회논문지
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• 제11권8호
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• pp.764-770
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• 2001

본 논문에서는 대용량의 퍼지 데이터를 고속으로 전송 및 추론하기 위해 새로운 PCI 버스 기반 병렬 퍼지 시스템을 제안한다. 많은 퍼지 데이터의 고속전송을 위해 PCI 9050 인터페이스를 사용하고, 병렬 퍼지 추론 시스템을 위한 병렬 퍼지 모듈들을 FPGA로 설계하여 PCI 타겟 코어로서 병렬로 동작하게 한다. 여기서 소속함수들의 각 요소와 전건부 또는 후건부부분의 병렬화을 고려하여 제안된 시스템을 VHDL을 사용하여 설계 및 구현하였다. 제안된 시스템은 실시간에 고속의 퍼지추론을 요하는 시스템 또는 대용량 인공위성 영상 데이터의 패턴 인식 등과 같이 다수의 전건부, 후건부의 변수를 갖는 시스템에 활용될 수 있다.

• 전기학회논문지P
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• 제64권1호
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• pp.29-34
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• 2015

DC bus electrolytic capacitors are used in variety of equipments as smoothing element of the power converters because it has high capacitance for its size and low price. It is responsible for frequent breakdowns of many static converters and inverter drive systems. Therefore it is important to diagnosis monitoring the condition of an electrolytic capacitor in real-time to predict the failure of power converter. In this paper, the on-line remote diagnosis monitoring system for DC BUS electrolytic capacitors of power converter using low-cost type Zigbee communication modules is developed. To estimate the health status of the capacitor, the equivalent series resistor(ESR) of the component has to be determined. The capacitor ESR is estimated by using RMS computation using AC coupling method of DC link ripple voltage/current. The Zigbee communication-based experimental results show that the proposed remote DC capacitor diagnosis monitoring system can be applied to DC/DC converter and UPS successfully.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• 대한토목학회논문집
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• 제31권1D호
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• pp.33-42
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• 2011

본 연구는 부산광역시 시내버스 준공영제 시행에 따른 시내버스 교통사고 발생 유형 및 시내버스 운전자의 운전태도 변화 경향을 분석하고 이를 토대로 하여 교통사고 저감대책을 고찰한 바 그 결과는 다음과 같다. 첫째, 시내버스 준공영제 시행 전 후와 시행 후 시간이 경과함에 따른 교통사고는 전반적으로 감소하고 있는 것으로 나타났다. 둘째, 시내버스 준공영제 시행 전 후 시내버스 운전자의 교통법규 위반과 교통사고 감소에 가장 많은 영향을 끼친 요인으로는 안전운전 의무 불이행 위반 감소와 고용 안정으로 나타났다. 셋째, PROXSCAL 분석 결과에 따른 교통사고 저감대책을 마련, 제시할 수 있었다.

• 한국정보통신학회논문지
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• 제16권10호
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• pp.2261-2266
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• 2012

일반적인 버스 시스템 구조는 공용버스 내에 여러 개의 마스터와 슬레이브, 아비터 그리고 디코더 등으로 구성되어 있다. 복수의 마스터가 동시간대에 버스를 이용할 수 없으므로, 아비터는 이를 중재하는 역할을 수행한다. 아비터가 어떠한 중재방식을 선택하는가에 따라 버스 사용의 효율성이 결정된다. 기존의 중재 방식에는 Fixed Priority 방식, Round-Robin 방식, TDMA 방식, 로터리 방식 등이 연구되고 있다. 본 논문에서는 데이터 트래픽 집중에 따른 Fixed Priority, Round Robin, TDMA, 로터리 방식에 대하여 성능을 분석해 보고, 성능개선을 위한 방법을 제안하려고 한다.

• 한국정보통신학회논문지
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• 제16권9호
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• pp.2009-2014
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• 2012

일반적인 버스 시스템 구조는 공용버스 내에 여러 개의 마스터와 슬레이브, 아비터 그리고 디코더 등으로 구성되어 있다. 복수의 마스터가 동시간대에 버스를 이용할 수 없으므로, 아비터는 이를 중재하는 역할을 수행한다. 아비터가 어떠한 중재방식을 선택하는가에 따라 버스 사용의 효율성이 결정된다. 기존의 중재 방식에는 Fixed Priority방식, Round-Robin 방식, TDMA 방식, 로터리 방식 등이 연구되고 있다. 본 논문에서는 최근에 개발된 TDMA 방식과 로터리 방식에 대하여 성능을 비교해 보고, 성능개선을 위한 방법을 제안하려고 한다.