• Journal of information and communication convergence engineering
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• v.9 no.4
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• pp.428-430
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• 2011

Recent semiconductor design technology has been substantially developed that we can design a micro-system on a chip as well as implementing an application specific IC in an FPGA. SPARTAN-3E developed by Xilinx is equipped with an FPGA that holds as much as 500 thousand transistors connected with MicroBlaze softcore microprocessor bus system. In this paper, we discuss a method of implementing an embedded system using the SPARTAN-3E. We also explain the peripherals and the bus protocols and the expandability of this kind of embedded systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.812-822
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• 1997

In this paper, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the priority scheme is implemented in both input and output queues. We analyze packet delay of both input and output queues. In the analysis, we consider to stations with asymmetric arrival rates. Although we make some approximations in the analysis, the numerical results show good agreements with the simulation results.

• Proceedings of the Korean Society of Computer Information Conference
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• 2023.01a
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• pp.409-410
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• 2023

본 논문에서는 새로운 교통신호 시스템에 적합한 레이더와 Can-bus 통신방식을 이용한 새로운 차세대 신호등 방식을 제시한다. 이 방식은 서로 보이지 않는 신호등을 통과하는 사람과 자동차가 보이지 않는 곳에서 사람과 자동차의 진입 정보를 신호등에 전송해 사고를 예방하는 시스템이다.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.23 no.1
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• pp.97-111
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• 2024

Developing countries and small local governments face financial constraints, limiting the adoption of their own bus information systems. However, despite poor social infrastructure and low income levels, developing countries have a high smartphone penetration rate, and the distribution and usage of online content and social media are widespread. Smartphones, equipped with GPS sensors, cameras, and other location-based information collection capabilities, can replace expensive on-site terminals. This study aims to replace expensive on-site terminals with smartphones, develop a center system based on cloud servers, and establish an extensible Open BIS (Bus Information System) service and platform that can be applied anywhere. The goal is to formulate a business model in the process.

• Journal of the Korea Society of Computer and Information
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• v.27 no.7
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• pp.165-175
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• 2022

The objective of this study is to identify the relationships among app attribution(perceived usefulness, design, information quality, and mobility), user satisfaction, trust, and continuous use intention of bus information apps; The structural equation of AMOS 21.0 was used to test the hypothesis of this study. The results of the analysis are as follows. First, perceived usefulness, design, information quality, and mobility positively impact user satisfaction. Second, only mobility has a positive effect on trust, but the remaining perceived usefulness, design, and information quality have no effect at the significance level of 5%. Third, user satisfaction has a positive impact on trust and continuous use intention. Fourth, trust has a positive impact on continuous use intention. Therefore, it was confirmed that the characteristics of the bus information mobile app are important influencing factors for the improvement of user satisfaction, trust, and continuous use intention. Local governments and bus companies will be able to establish strategic directions for the activation of bus information mobile apps. The limitation of this study is that it is somewhat lacking in generalizing the study results, so future research needs to focus on improving this part.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.56-62
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• 2002

A new high speed and low voltage swing on-chip BUS using threshold voltage swing driver and dual sense amplifier receiver is proposed. The threshold voltage swing driver reduces the rising time in the bus to 30% of the full CMOS inverter driver and the dual sense amplifier receiver increases twice the throughput. of the conventional reduced-swing buses using sense amplifier receiver. With threshold voltage swing driver and dual sense amplifier receiver combined, approximately 60% speed improvement and 75% power reduction are achieved in the proposed scheme compared to the conventional full CMOS inverter for the on-chip bus.

• Proceedings of the KSRS Conference
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• 2005.10a
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• pp.637-640
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• 2005

In the development of a electronic system for a optical payload comprising mainly EOS(Electro-Optical Sub-system) and PDTS(Payload Data Transmission Sub-system), many aspects should be investigated and discussed for the easy implementation, for th e higher reliability of operation and for the effective ness in cost, size and weight as well as for the secure interface with components of a satellite bus, etc. As important aspects the interfaces between a satellite bus and a payload, and some design features of the CEU(Camera Electronics Unit) inside the payload are described in this paper. Interfaces between a satellite bus and a payload depend considerably on whether t he payload carries the PMU(Payload Management Un it), which functions as main controller of the Payload, or not. With the PMU inside the payload, EOS and PDTS control is performed through the PMU keep ing the least interfaces of control signals and primary power lines, while the EOS and PDTS control is performed directly by the satellite bus components using relatively many control signals when no PMU exists inside the payload. For the CEU design the output channel configurations of panchromatic and multi-spectral bands including the video image data inter face between EOS and PDTS are described conceptually. The timing information control which is also important and necessary to interpret the received image data is described.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.71-79
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• 2004

Packet-type data transmission is characterized by the continuous transmission of massive data with relatively constant rate. In such transmission, the dynamic power consumed on buses is influenced by the sequence of transmitted data. A new coding scheme called Sequence-Switch Coding (SSC) is proposed in this paper. SSC reduces the number of bus transitions in the transmission of packet-type data by changing the sending order of the data. Some simple algorithms are presented, In. The simulation results show that SSC outperforms the well-known Bus-Invert Coding with these algorithms. SSC is not a specific algerian but a method to reduce the number of bus-transitions. There could be lots of algorithms for realizing SSC. The variety of SSC algorithms provides circuit designers a wide range of trade-off between performance and circuit complexity.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.1-10
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• 1997

We present an approach to high-level synthesis for a specific target architecture-partitioned bus architecture. In this approach, we have specific goals of minimizing data transfer length and number of buses in addition to common synthesis goals such as minimizing number of control steps and satisfying given resource constraint. Minimizing data transfer length and number of buses can be very important design goals in the era of deep submicron technology in which interconnection delay and area dominate total delay and area of the chip to be designed. in partitioned bus architecture, to get optimal solution satisfying all the goals, partitioning of operation nodes among segments and ordering of segments as well as scheduling and allocation/binding must be considered concurrently. Those additional goals may impose much more complexity on the existing high-level synthesis problem. To cope with this increased complexity and get reasonable results, we have employed two ideas in ur synthesis approach-extension of the target architecture to alleviate bus requirement for data transfer and adoption of genetic algorithm as a principal methodology for design space exploration. Experimental results show that our approach is a promising high-level synthesis mehtodology for partitioned bus architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.1-6
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• 2009

This paper presents new high speed architecture using DBI(Data Bus Inversion) in DRAM. The DBI is one of the general methods in the signaling circuits to decrease the known problems such as SSO and LSI. Many architectures have been proposed to reduce the number of transitions on the data bus. In this paper, the DBI, the Analog Majority Voter (AMV) circuit, the GIO control circuit and the SSO algorithm are newly proposed. The power consumption can he reduced with the help of direct GIO inversion method and the eye diagram of data can be increased to 40ps. Using proposed DBI scheme can produce almost stable SI of DQs against high speed operation. The DBI is fabricated in 90nm CMOS Technology.