• Proceedings of the Korea Information Processing Society Conference
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• 2002.11a
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• pp.535-538
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• 2002

InfiniBand is a switched-fabric architecture for next generation I/O systems and data centers. The InfiniBand Architecture (IBA) promises to replace bus-based architectures, such as PCI, with a switched-based fabric whose benefits include higher performance, higher RAS (reliability, availability, scalability), and the ability to create modular networks of servers and shared I/O devices. The switched-fabric InfiniBand consists of InfiniBand subnets with channel adapters, switches, and routers. In order to fully grasp the operational characteristics of InfiniBand architecture (IBA) and use them in ongoing design specification, simulation of subnet management of IBA is inevitable. In this paper, thus, we implement an IBA simulator and test some practical sample networks using it. The simulator shows the flow of operation by which the correctness and effectiveness of the system can be verified.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.9-19
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• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of KIBIM
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• v.8 no.4
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• pp.23-33
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• 2018

Recently, the industry actively adopts the cutting-edge technologies of the fourth industrial revolution and uses them to enhance the productivity and service of mass-customization. The manufacturing industry is creating new processes and business models by achieving digital transformations through a lean start-up approach aimed at achieving the highest customer satisfaction with minimal resources. Although attempts are made to manufacture the building by introducing the latest technology in architecture, it is applied sporadically, not as an integrated system, in the entire phase of the architectural project. This paper analyzes the changes in the construction industry through the application of core technologies of the fourth industrial revolution. Design processes are analyzed for the digital transformation of the construction industry by case study of advanced architectural design practice. A novel design concept model 'Architectural lean startup' is proposed by combining the architectural process and the lean start up method. Through the design of the bus stop based on the architectural lean startup concept, it is confirmed that the designer repeats the 'Generate-Test-Analysis' to develop the design and generate the final result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.86-92
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• 2011

In this paper, we propose a novel hardware MPI(Message Passing Interface) unit which supports message passing in multiprocessor system which use distributed memory architecture. MPI Hardware unit processes data synchronization, transmission and completion, and it supports processor non-blocking operation so it reduces overhead according to synchronization. Additionally, MPI hardware unit combines ready entry, request entry, reserve entry which save and manage the synchronized messages and performs the multiple outstanding issue and out of order completion. According to BFM(Bus Functional Model) simulation result, the performance is increased by 25% on many to many communication. After we designed MPI unit using HDL, with synopsys design compiler we synthesized, and for synthesis library we used MagnaChip $0.18{\mu}m$. And then we making prototype chip. The proposed message transmission interface hardware shows high performance for its increase in size. Thus, as we consider low-cost design and scalability, MPI hardware unit is useful in increasing overall performance of embedded MPSoC(Multi-Processor System-on-Chip).

• Journal of KIISE:Software and Applications
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• v.35 no.2
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• pp.91-104
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• 2008

Service-Oriented Computing (SOC) is the development method that published services are selected and composed at runtime to deliver the expected functionality to service clients. SOC should get maximum benefits not only supporting business agility but also reducing the development time. Services are selected and composed at runtime to improve the benefits. However, current programming language, SOC platforms, business process modeling language, and tools support either manual selection or static binding of published services. There is a limitation on reconfiguring and redeploying the business process to deliver the expected services to each client. Therefore, dynamic selection is needed for composing appropriate services to service clients in a quick and flexible manner. In this paper, we propose Dynamic Selection Handler (DSH) on ESB. we present a design method of Dynamic Selection Handler which consists of four components; Invocation Listener, Service Selector, Service Binder and Interface Transformer. We apply appropriate design patterns for each component to maximize reusability of components. Finally, we describe a case study that shows the feasibility of DSH on ESB.

• Journal of The Korea Institute of Healthcare Architecture
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• v.25 no.4
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• pp.61-70
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• 2019

Purpose: This study aims to find directions to improve the barrier-free (BF) certification criteria by assessing the current BF certification system, which is used as a method to improve access to passenger facilities and as a method for universal design planning, and by comparing BF certified facilities with non-BF certified facilities. Methods: This study assesses 20 BF certified facilities and 39 non-BF certified facilities, which were constructed in 2005 and onwards. The results of the assessment are compared and analyzed based on the following three categories: railway stations, urban railway stations and bus terminals. Results: The results of the analysis show that the total scores of the BF certified facilities are higher than those of the facilities that were not BF certified, indicating that the BF certification system is effective. Implication: However, there are some criteria items showing higher scores in facilities that are not BF certified than in BF certified facilities. This suggests the need to improve the BF certification criteria.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.11
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• pp.527-539
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• 2008

This paper presents a performance estimation technique based on queuing analysis for on-chip bus matrix architectures of Multi-Processor System-on-Chips(MPSoCs). Previous works relying on time-consuming simulation are not able to explore the vast design space to cope with increasing time-to-market pressure. The proposed technique gives accurate estimation results while achieving faster estimation time than cycle -accurate simulation by order of magnitude. We consider the followings for the modeling of practical memory subsystem: (1) the service time with the general distribution instead of the exponential distribution and (2) multiple-outstanding transactions to achieve high performance. The experimental results show that the proposed analysis technique has the accuracy of 94% on average and much shorter runtime ($10^5$ times faster at least) compared to simulation for the various examples: the synthetic traces and real-time application, 4-channel DVR.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.4
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• pp.55-60
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• 2013

Smart client is a term describing an application environment which delivers applications over a web HTTP connection and does not require installation and/or updates. The term "Smart Client" is meant to refer to simultaneously capturing the benefits of a "thin client" (zero-install, auto-update) and a "fat client" (high performance, high productivity). A "Smart Client" application can be created in several very different technologies. Over the past few years, ITS has started to move towards smart clients, also called rich clients. The trend is a move from traditional client/server architecture to a Web-based model. More similar to a fat client vs. a thin client, smart clients are Internet-connected devices that allows a user's local applications to interact with server-based applications through the use of Web services. Smart Client applications in BIT bridge the gap between web applications and desktop applications. They provide the benefits of a web applicationwhile still providing the snappy look and feel inherent to desktop applications.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.465-474
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• 2005

For high density SoC design, on-chip communication based on bus interconnection encounters bandwidth limitation while an NoC(Network-on-Chip) approach suffers from unacceptable complexity in its Implementation. This paper introduces a new on-chip communication protocol, SNP (SoC Network Protocol) to overcome these problems. In SNP, conventional on-chip bus signals are categorized into three groups, control, address, and data and only one set of wires is used to transmit all three groups of signals, resulting in the dramatic decrease of the number of wires. SNP efficiently supports master-master communication as well as master-slave communication with symmetric channels. A sequencing rule of signal groups is defined as a part of SNP specification and a phase-restoration feature is proposed to avoid redundant signals transmitted repeatedly over back-to-back transactions. Simulation results show that SNP provides about the same bandwidth with only $54\%$ of wires when compared with AMBA AHB.

• Journal of The Korean Digital Architecture Interior Association
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• v.1 no.1
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• pp.59-66
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• 2001

The purpose of this study is to improve productivity of architectural space planning(A.S.P,) by computer system and to optimize ASP. A searching algorithm is the best way to slave optimized A.S.P. Because architectural design is too many various site situations and client's demands to specify the general solving methods. This method seek the best design case in all possibility and to be modeled as this; Seongbukgu's case that is city structure former times negative by in facilities utilization of the near street limit. But, case of Gangnamgu and Songpagu is thought that environment and utilization etc. of area life of old people are affinity with quality of life environment of old people when see that is using various area facilities using electric railway and a bus etc. actively. It is looked by the other that individual's special quality uses area facilities according to life partner's existence and nonexistence and family composition and existence and nonexistence of profession and distinction of sex. Show difference of external behavior according to public garden and market and supermarket and welfare facilities etc.'s location in dwelling environment of area and relation about facilities of area has been formed and old people and dwelling environment of area can know that is that do interaction. Environment that access about facilities may have to be easy, and can live that communicating closely with area's inhabitantses may have to consist so that old people may can run various external life.. Notions of the evaluated value is an profit(+) and expense(-) that decide design intention. To adapt real planning, 1. A raster type space cell has logical site informations. 2. To be evaluate various factor. 3. To reflect operator's design mind, they should add an extra weight on evaluated value.