• Title/Summary/Keyword: Burst mode

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Burst Test and Finite Element Analysis for Failure Pressure Evaluation of Nuclear Power Plant Pipes (원전 배관 손상압력 평가를 위한 파열시험 및 유한요소해석)

  • Yoon, Min Soo;Kim, Sung Hwan;Kim, Taesoon
    • Journal of the Korean Society of Safety
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    • v.30 no.1
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    • pp.144-149
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    • 2015
  • This study aims to quantitatively evaluate failure pressure of wall-thinned elbow under combined load along with internal pressure, by conducting real-scale burst test and finite element analysis together. For quantitative evaluation, failure pressure data was extracted from the real-scale burst test first, and then finite element analysis was carried out to compare with the test result. For the test, the wall-thinning defect of the extrados or intrados inside the center of 90-degree elbow was considered and the loading modes to open or close the specimen maintaining a certain load or displacement were applied. Internal pressure was applied until failure occurred. As a result, when the bending load was applied under the load control condition, the intrados of the defect was more affected by failure pressure than the extrados, and the opening mode was more vulnerable to failure pressure than the closing mode. When the bending load was applied under the displacement control, it was hardly affected by failure pressure though it was slightly different from the defect position. The result of the finite element analysis showed a similar aspect with the test. Moreover, when major factors such as material properties and pipeline thickness were calibrated to accurate values, the analytical results was more similar to the test results.

Design of a convolutional encoder and viterbi cecoder ASIC for continuous and burst mode communications (연속 및 버스트모드 통신을 위한 길쌈부호기와 비터비복호기 ASIC 설계)

  • 장대익;김대영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.4
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    • pp.984-995
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    • 1996
  • Data errors according to the various noises caused in the satellite communication links are corrected by the Viterbi decoding algorithm which has extreme error correcting capability. In this paper, we designed and implemented a convolutional encoder and Viterbi decoder ASIC which is used to encode the input data at the transmit side and correct the errors of the received data at the receive side for use in the VSAT communication system. And this chip may be used in any BPSK, QPSK, or OQPSK transmission system. The ambiguity resolver corrects PSK modem ambiguities by delaying, interting, and/or exchanging code symbol to restore their original sequence and polarity. In case of previous decoding system, ambiguity state(AS) of data is resolved by external control logic and extra redundancy data are needed to resolve AS. But, by adopting decoder proposed in this paper, As of data is resolved automatically by internal logic of decoder in case of continuous mode, and by external As line withoug extra redudancy data in burst mode case. So, decoding parts are simple in continuous mode and transmission efficiency is increased in bust mode. The features of this chip are full duplex operation with independent transmit and receive control and clocks, start/stop inputs for use in burst mode systems, loopback function to verify encoder and decoder, and internal or external control to resolve ambinguity state. For verification of the function and performance of a fabricated ASIC chip, we equiped this chip in the Central and Remote Earth Station of VSAT system, and did the performance test using the commerical INTELSAT VII under the real satellite link environmens. The results of test were demonstrated the superiority of performance.

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A 2.5 Gb/s Burst-Mode Clock and Data Recovery with Digital Frequency Calibration and Jitter Rejection Scheme (디지털 주파수 보정과 지터 제거 기법을 적용한 2.5 Gb/s 버스트 모드 클럭 데이터 복원기)

  • Jung, Jae-Hun;Jung, Yun-Hwan;Shin, Dong Ho;Kim, Yong Sin;Baek, Kwang-Hyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.7
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    • pp.87-95
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    • 2013
  • In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

Preamble Detector and Synchronization in the TDD mode for BWA System

  • Shin Eun-jeong;Kim, In-Hyoung;Ann, Jae-Young;Kim, Eun-Bae
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.413-416
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    • 2002
  • On the TDD system, the uplink and downlink transmission share the same frequency but are seperated in time. In this paper we just consider the uplink transmission. The BWA system in this paper should be accepted the adaptive modulation. Each uplink burst shall begin with an uplink preamble. The reception of an uplink burst is the most challenging from a synchronization perspective. The burst detection, power estimation, symbol synchronization and carrier synchronization should be obtained from the preamble. It will be shown in this paper, how can get a burst detection by preambles and extract the synchronization parameter from preamble.

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A Burst Error Correction Decoding Algorithm in TCM on Mobile Communications (이동통신에서 TCM의 연집에러 정정을 위한 복호방식)

  • 이영천;김종일;이명수;홍대식;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.9
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    • pp.1020-1028
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    • 1992
  • In this paper, a burst-error-correcting adaptive decoding in TCM(Trellis Coded Modulation) is presented that combines maximun-likelihood decoding with a burst error detection scheme. The decoder usually operates as a Viterbi decoder and switches to a burst-error-correcting mode whenever error patterns uncorrectable by Viterbi decoder are detected. It is demonstrated that TCM using adaptive decoding method outperforms a traditional TCM on the multi-path fading channels that are busty in nature, which are like the channel environments of mobile communications.

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A Study on the Design of Green Mode Power Switch IC (그린 모드 파워 스위치 IC 설계에 관한 연구)

  • Lee, Woo-Ram;Son, Sang-Hee;Chung, Won-Sup
    • Journal of IKEEE
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    • v.14 no.2
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    • pp.1-8
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    • 2010
  • In this paper, Green Mode Power IC is designed to reduce the standby power. The proposed and designed IC works for the Switch Mode Power Supply(SMPS) and has the function of PWM. To reduce the unnecessary electric power, burst mode and skip mode section are introduced and controlled by external power MOSFET to diminish the standby power. The proposed IC is designed and simulated by KEC 30V-High Voltage 0.5um CMOS Process. The structure of proposed IC is composed of voltage regulator circuit, voltage reference circuit, UVLO(Under Voltage Lock out) circuit, Ibias circuit, green circuit, PWM circuit, OSC circuit, protection circuit, control circuit, and level & driver circuit. Measuring the current consumption of each block from the simulation results, 1.2942 mA of the summing consumption current from each block is calculated and ot proved that it is within the our design target of 1.3 mA. The current consumption of the proposed IC in this paper is less than a half of conventional ICs, and power consumption is reduced to the extent of 1W in standby mode. From the above results, we know that efficiency of proposed IC is superior to the previous IC.

An Automatic Threshold Control Circuit Adaptive to Burst Optical signal Levels (버스트 광 신호 레벨 적응형 기준레벨 자동 발생회로)

  • 기현철
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.12
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    • pp.24-30
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    • 2003
  • In this paper, we proposed an adaptive ATC(Automatic Threshold Control) circuit with more decreased settling time by improving the structure of the peak detector. We showed that it could reduce a good deal of the settling time because it showed less than half the error voltage ratio that the ATC circuit with conventional structure showed in analysis. We also designed a burst-mode ATC circuit for the 1.25Gbps EPON system using a commercial foundry. It produced the reference levels in very short time, 6㎱ in 40 ㏈ input dynamic range.

A Novel Flyback Converter for Low Standby Power Consumption (대기전력저감을 위한 플라이백컨버터)

  • Chung, Bong-Gun;Jang, Sang-Ho;Kim, Eun-Soo;Choi, Mun-Gi;Kye, Moon-Ho
    • The Transactions of the Korean Institute of Power Electronics
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    • v.14 no.4
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    • pp.299-306
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    • 2009
  • Recently, although the power consumption of the flyback converter at the light load and standby power load was minimized by the burst mode operation of PWM IC, flyback converter has still the low efficiency characteristics by the high magnetizing current flowing through magnetizing inductance of transformer. This paper proposes a novel flyback converter with an improved efficiency characteristics and the reduced magnetizing current at the light load and standby power load. Prototype of the 70W multi-output flyback converter for an auxiliary power module of 50 inch PDP TV is built and the experimental results are described.