• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.113-113
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• 2016

반도체 웨이퍼 패키지 공정에는 솔더 범프용으로 주석-은 합금 도금액이 사용되어 왔다. 최근, 주석-은 도금 피막중의 은 함량의 불균일성, 불용성 양극의 사용에 의한 전압 상승. 은의 도금 치구에의 석출, 리플로 후의 보이드의 형성 등의 문제로 인하여 주석 단독 금속 도금에 의한 범프 형성이 실용화되었다. 본 연구에서는, 범프용 주석 도금액에서의 전류밀도, 금속이온의 농도, 유리산의 농도 및 첨가제의 농도가 범프 두께 균일성에 미치는 영향을 조사하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.366-369
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• 2003

The vertical fountain plating system with the point contact has been used in semiconductor industry. But the plating shape in the opening of photoresist becomes gradated shape, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. So, we designed the tilted electrode ring contact to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha$-step. A photoresist was coated to a thickness of $60{\mu}m$ and vias were patterned by a contact aligner After via opening, solder layer was electroplated using the fountain plating system and the tilted electrode ring contact system. In $\alpha$-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were ${\pm}16%,\;{\pm}3.7%$ respectively. In this study, we could get high uniformity bumps by the tilted electrode ring contact system. So, tilted electrode ring contact system is expected to improve workability and yield in module process.

• Journal of Korea Game Society
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• v.8 no.1
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• pp.71-77
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• 2008

The geometric structure constructs terrain from height map and non-periodically tiling with Wang tile for the detail description. It will be able to express detail bump using parallax mapping to add decal data together with height data in tile. We solve the problem when the real-time rendering and propose improving of parallax mapping for the terrain.

• Journal of the Korean Geotechnical Society
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• v.33 no.11
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• pp.35-43
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• 2017

In this study, the pull-out resistance behavior of the anchor with the bump type resistors at the anchor body was experimentally investigated. In the model tests, the pull-out resistance was measured by pulling out the anchor at a constant speed. Anchor body was installed in the center of the circular sand tank. Pull-out tests were conducted for 10 conditions. The anchor type (existence of the resistor), the friction conditions of the anchor body surface ($1/3{\phi}$, $2/3{\phi}$, ${\phi}$), the bump type resistor set number (1set, 2set, 4set), and the height of resistors (0.05d, 0.10d, 0.20d) were varied. The load-displacement relationship for each conditions was measured during the pull-out tests at a constant speed (1 mm/min). Maximum pull-out length was 80 mm. As a result, the pull-out behavior of the friction type anchor and the expansion type anchor was different. As the number of resistor increased, the maximum pull-out resistance increased and the residual pull-out resistance ratio increased significantly, which were at 171~591 percent larger than that of the friction type anchor.

• Korean Journal of Optics and Photonics
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• v.19 no.5
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• pp.376-380
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• 2008

This paper presents the Projection Moire method using a line scan camera. The high resolution feature of a line scan camera makes it possible to scan an image quickly, thus enabling a much quicker 3D profile. This method uses a high resolution line scan camera making it possible to scan an image at high speed simultaneously measuring the 3D profile of a large FOV. When using a high resolution scan camera, a full FOV is scanned, thus requiring just one movement of a projection grating. As a result, the number of grating movements is reduced drastically. The end result is a faster and more accurate 3D measurement. Moving the grating too quickly causes vibration in the imaging system, which will normally be required to apply a stitching technique when using an area scan camera. However the technique is not required when using a line scan camera. Compared with the previous techniques, it has the advantages of simple hardware without moving mechanical parts - single exposure for obtaining three-dimensional information. A method using a high resolution line scan camera can be used in mass production to measure the bump height of wafers or the bump height of package substrates.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.21-26
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• 2002

Solder flip chip bumping and subsequent coining processes on PCB were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCB has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation : (1) elastic deformation at early stage, (2) linear increase of applied load, and (3) rapid increase of applied load. In order to reduce applied loads for coining solder bumps on PCB, effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Among the effect of two factors on coining loads, it was found that process temperature had more significant effect to reduce applied coining loads during the coining process. Lower coining loads were needed to prevent substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying loads. For flip chip assembly, 97Pb/Sn flip chip bumped devices were successfully assembled on organic substrates with 37Pb/Sn coined flip chip bumps.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.829-834
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• 2003

Many types of omnidirectional wheels with passive rollers have gaps between rollers. Since these gaps cause a wheel to make discontinuous contact with the ground, they lead to vertical and/or horizontal vibrations during wheel operation. In addition, the radii of passive rollers are related to the height of a bump an omnidirectional wheel can surmount. In this research a new design of the alternate wheel is proposed. Because this wheel makes continuous contact with the ground and has alternating large and small rollers around the wheel, it is termed a continuous alternate wheel (CAW). In this paper a design procedure is also presented to determine the optimum number of rollers, the radii of rollers and the inside inclination angle of an outer roller for given design specifications. The CAW based on this design is compared to the existing alternate wheels in terms of design. Finally, an actual continuous alternate wheel is constructed to verify validity of the design guidelines.

• Journal of the Korean Society of Industry Convergence
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• v.3 no.1
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• pp.69-75
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• 2000

Multichip packages are comprised of dissimilar materials which expand at different rates on heating. The differential expansion must be accommodated by the various structural elements of the package. A types of heat exposures occur operation cycles. This study presents a finite element analysis simulation of flip-chip among multichip. The effects of geometries and material properties on the reliability were estimated during the analysis of temperature and thermal stress of flip-chip. From the results, it could be obtained that the more significant parameters to the reliability of flip-chip arc chip power cycle, heat convection and height of solder bump.

• Journal of Welding and Joining
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• v.25 no.3
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• pp.45-50
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• 2007

The present study is devoted to investigate the transient flow and to estimate the filling time fur underfill process by using the numerical model established on the fluid momentum equation. For optimization of the design and selection of process parameters, this study extensively presents an estimation of the filling time in the view points of some important factors related to underfill materials and flip-chip geometry. From the results, we conclude that the filling time changes with respect to the under fill materials because of different viscosity, surface tension coefficient and contact angle. It reveals that, as the gap height increases, the filling time decreases substantially, and goes to the saturated values.