• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.128.1-128.1
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• 2016

Nitrided-metal gates on the high-${\kappa}$ dielectric material are widely studied because of their use for sub-20nm semiconductor devices and the academic interest for the evanescent states at the Si/insulator interface. Issues in these systems with the Si substrate are the electron mobility degradation and the reliability problems caused from N defects that permeates between the Si and the $SiO_2$ buffer layer interface from the nitrided-gate during the gate deposition process. Previous studies proposed the N defect structures with the gap states at the Si band gap region. However, recent experimental data shows the possibility of the most stable structure without any N defect state between the bulk Si valence band maximum (VBM) and conduction band minimum (CBM). In this talk, we present a new type of the N defect structure and the electronic structure of the proposed structure by using the first-principles calculation. We find that the pair structure of N atoms at the $Si/SiO_2$ interface has the lowest energy among the structures considered. In the electronic structure, the N pair changes the eigenvalue of the silicon-induced gap state (SIGS) that is spatially localized at the interface and energetically located just above the bulk VBM. With increase of the number of N defects, the SIGS gradually disappears in the bulk Si gap region, as a result, the system gap is increased by the N defect. We find that the SIGS shift with the N defect mainly originates from the change of the kinetic energy part of the eigenstate by the reduction of the SIGS modulation for the incorporated N defect.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.37-43
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• 2008

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program/erase (P/E) speed, reliability of memory device on interface trap between Si substrate and tunneling oxide and bulk trap in nitride layer were investigated using charge pumping method which has advantage of simple and versatile technique. We analyzed different SANOS memory devices that were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SANOS cell transistors with larger capture cross section and interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. The data retention was deteriorated as increasing P/E cycling number but not coincides with interface trap increasing tendency. This result once again confirmed that interface trap independence on data retention. And the result on different program method shows that HCI program method more degraded by locally trapping. So, we know as a result of experiment that analysis the SANOS Flash memory characteristic using charge pumping method reflect the device performance related to interface and bulk trap.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.24 no.6
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• pp.246-251
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• 2014

Recent studies have shown methods of improving solar cell efficiency. Especially on single crystalline silicon wafer which is high-efficiency solar cell material that has been widely studied. Interstitial oxygen (Oi) is the main impurity in the Czochralski (Cz) growing method, and excess of this can form precipitates during cell fabrication. We have demonstrated the effect of Oi impurity and oxygen precipitation concentration of the wafer on Cz-silicon solar cell efficiency. The result showed a decrease in cell efficiency as Oi and oxygen precipitation increase. Moreover, we have found that the critical point of [Oi] to bring higher cell efficiency is at 14.5 ppma in non-existent Bulk Micro Defect (BMD).

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.63-67
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• 2008

3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to $30{\mu}m\;or\;50{\mu}m$ thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.661-669
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• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.276-279
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• 2004

Plasma enhanced chemical vapor deposition (PECVD) of silicon nitride (SiN) is a proven technique for obtaining layers that meet the needs of surface passivation and anti-reflection coating. In addition, the deposition process appears to provoke bulk passivation as well due to diffusion of atomic hydrogen. This bulk passivation is an important advantage of PECVD deposition when compared to the conventional CVD techniques. A further advantage of PECVD is that the process takes place at a relatively low temperature of 300t, keeping the total thermal budget of the cell processing to a minimum. In this work SiN deposition was performed using a horizontal PECVD reactor system consisting of a long horizontal quartz tube that was radiantly heated. Special and long rectangular graphite plates served as both the electrodes to establish the plasma and holders of the wafers. The electrode configuration was designed to provide a uniform plasma environment for each wafer and to ensure the film uniformity. These horizontally oriented graphite electrodes were stacked parallel to one another, side by side, with alternating plates serving as power and ground electrodes for the RF power supply. The plasma was formed in the space between each pair of plates. Also this paper deals with the fabrication of multicrystalline silicon solar cells with PECVD SiN layers combined with high-throughput screen printing and RTP firing. Using this sequence we were able to obtain solar cells with an efficiency of 14% for polished multi crystalline Si wafers of size 125 m square.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.429-429
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• 2012

To investigate the gettering effect of B-doped n-type monocrystalline silicon wafer, we made the p-n junction by diffusing boron into n-type monocrystalline Si substrate and then oxidized the boron doped n-type monocrystalline silicon wafer by in-situ wet and dry oxidation. After oxidation, the minority carrier lifetime was measured by using microwave photoconductance and the sheet resistance by 4-point probe, respectively. The junction depth was analyzed by Secondary Ion Mass Spectrometry (SIMS). Boron diffusion reduced the metal impurities in the bulk of silicon wafer and increased the minority carrier lifetime. In the case of wet oxidation, the sheet resistance value of ${\sim}46{\Omega}/{\Box}$ was obtained at $900^{\circ}C$, depostion time 50 min, and drive-in time 10 min. Uniformity was ~7% at $925^{\circ}C$, deposition time 30 min, and drive-in time 10 min. Finally, the minority carrier lifetime was shown to be increased from $3.3{\mu}s$ for bare wafer to $21.6{\mu}s$ for $900^{\circ}C$, deposition 40 min, and drive-in 10 min condition. In the case of dry oxidation, for the condition of 50 min deposition, 10 min drive-in, and O2 flow of 2000 SCCM, the minority carrier lifetime of 16.3us, the sheet resistance of ${\sim}48{\Omega}/{\Box}$, and uniformity of 2% were measured.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.122.1-122.1
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• 2011

Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.

• Journal of the Korean Ceramic Society
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• v.45 no.2
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• pp.99-104
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• 2008

Zeta potential, sedimentation bulk density and rheology in the dispersion system have been studied in terms of solid loading (40-55 vol%), and types of additives. Ammonium polymethacrylate, glycerol, ethoxylated acetylenic diol, and polyvinyl alcohol have been used as the dispersant, cryo-protectant, surfactant, and binder, respectively. Sedimentation density greatly increased upon adding dispersant; the effect was more pronounced with ionic alumina suspension compared with covalent silicon carbide. With further addition of cryo-protectant and surfactant to dispersant, the sedimentation density increased somewhat. The suspension viscosity generally behaviored in an opposite manner to the sedimentation density, i.e., high sedimentation gave low high-shear viscosity, indicative of low order structure formation in the suspended particles. Shear rate rheology in shear rate of $2-300\;sec^{-1}$ showed a shear thinning and its onset began at similar shear rate (${\sim}100\;sce^{-1}$), regardless of solid loading.

• Current Photovoltaic Research
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• v.6 no.1
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• pp.27-30
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• 2018

The dependency of the electrical characteristics of silicon solar-cells on the depth of damaged layer induced by wire-sawing process was investigated. To compare cell efficiency with residual sawing damage, silicon solar-cells were fabricated by using as-sawn wafers having different depth of saw damage without any damaged etching process. The damaged layer induced by wire-sawing process in silicon bulk intensely influenced the value of fill factor on solar cells, degrading fill factor to 57.20%. In addition, the photovoltaic characteristics of solar cells applying texturing process shows that although the initial depth of saw-damage induced by wire-sawing process was different, the value of short-circuit current, fill-factor, and power-conversion-efficiency have an almost same, showing ~17.4% of cell efficiency. It indicated that the degradation of solar-cell efficiency induced by wire-sawing process could be prevented by eliminating all damaged layer through sufficient pyramid-surface texturing process.