• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.21-29
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• 2020

The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.1-10
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• 2011

There are the large overhead of block erase and page write operations in NAND flash memory, though it has low power consumption, cheap prices and a large storage. Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, so rewriting operation require after erase operation. it cause performance decrease of NAND flash memory. Using SRAM buffer in traditional NAND flash memory, it can not only reduce effective write operation but also guarantee fast memory access time. In this paper, we proposed the small SRAM buffer management system for reducing overhead of NAND flash memory, that is, erase and write operations. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer with the small fetching block size and a fully associative spatial buffer with the large fetching block size. The temporal buffer have small fetching blocks that referenced from spatial buffer. When it happen write operations or erase operations in NAND flash memory, the related fetching blocks in temporal buffer include a page or a block are written in NAND flash memory at the same time. The writing and erasing counts in NAND flash memory can be reduced. According to the simulation results, although we have high miss ratios, write and erase operations can be reduced approximatively 58% and 83% respectively. Also the average memory access times are improved about 84% compared with the fully associative buffer with two sizes.

• Journal of the Korean Operations Research and Management Science Society
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• v.22 no.2
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• pp.139-151
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• 1997

An ATM switching system may be designed so that communications between processors of its control part can be performed via its switching network rather than a separate inter-processor communications (IPC) network. In such a system, there should be interfaces to convent IPC traffic from message format to cell format and vice versa, that is, mechanisms to perform the SAR (Segmentation And Reassembly) sublayer functions. In this paper, we concern the cell reassembly mechanism among them, mainly focussed on buffer management schemes. We consider a few alternatives to implement cell reassembly function block, namely, separated buffering, reserved buffering and shared buffering in this paper. In case of separated and reserved buffering, we employ a continuous time Markov chain for the performance evaluation of cell reassembly mechanism, judicially defining the states of the mechanism. Performance measures such as measage loss probability, mean number of message queued in buffer and average reassembly delay are obtianed in closed forms. In case of shared buffering, we compare the alternatives for implementing cell reassembly function block using simulation because it is almost impossible to analyze the mechanism of shared buffering by analytical modeling. Some illustrations are given for the performance analysis of the alternatives to implement cell reassembly function block.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1993.04a
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• pp.213-213
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• 1993

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1992.04b
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• pp.261-261
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• 1992

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1994.04a
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• pp.513-513
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• 1994

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1994.04a
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• pp.515-515
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• 1994

• ETRI Journal
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• v.27 no.1
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• pp.1-12
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• 2005

We propose a heuristic buffer management scheme that uses both positive and negative acknowledgments to provide scalability and reliability. Under our scheme, most receiver nodes only send negative acknowledgments to their repair nodes to request packet retransmissions while some representative nodes also send positive acknowledgments to indicate which packets can be discarded from the repair node's buffer. Our scheme provides scalability because it significantly reduces the number of feedbacks sent by the receiver nodes. In addition, it provides fast recovery of transmission errors since the packets requested from the receiver nodes are almost always available in their buffers. Our scheme also reduces the number of additional retransmissions from the original sender node or upstream repair nodes. These features satisfy the original goal of treebased protocols since most packet retransmissions are performed within a local group.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.04a
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• pp.294-296
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• 1996

JIT(just-in-time) 생산시스템은 제조라인의 재공품 재고량을 최소화하고, 필요한 품목을 적시에 필요한 양만큼만 생산하여 공급하는 것을 목적으로 한다. 이러한 시스템은 사용하는 칸반의 수에 따라 single-card kanban system과 two-card kanban system으로 구별할 수 있다. 또한 각 공정이 입력버퍼(input buffer)와 출력버퍼(output buffer)를 갖는 경우와 공정간에 하나의 버퍼를 갖는 경우로 나누어 볼 수 있다. 본 연구는 기계간의 물류(material handling)가 필요한 시점에 즉시 이루어진다는 가정하에 기계간 버퍼가 하나이고, 그 버퍼의 용량이 1인 경우의 single-card kanban의 효율적인 운용방안을 개발하였다. 본 연구의 목적은 생산지시칸반의 회수시기를 적절히 조절하여 생산라인의 이용효율(utilization)을 극대화하고자 하는 것이다. 칸반회수시기 결정을 위한 상황분석의 범위를 10대의 기계로 제한하여 시뮬레이션에 의해 분석하였다. 기존의 칸반운영방식과 생산라인에서의 재고를 최소화하는 운영 알고리듬, 그리고 생산기계의 효율을 최대화할 수 있는 운영 알고리듬을 개발하여 비교.분석하였다.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.462-466
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• 2010

A new buffer cache management scheme that aims at reducing power consumption in mixed HDD and NAND flash memory storage systems is presented. The proposed scheme reduces power consumption by considering different energy-consumption rate of storage devices, I/O operation type (read or write), and reference potential of cached blocks in terms of both recency and frequency. Simulation shows that the proposed scheme reduces power consumption by 18.0% on average and up to 58.9%.