• Journal of Korea Multimedia Society
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• v.6 no.1
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• pp.161-166
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• 2003

This paper presents a high gain LNA for a bluetooth application using 0.25$\mu\textrm{m}$ CMOS technology. The conventional one stage LNA has a low power gain. The presented one stage LNA using a cascode inverter LNA with a voltage reference and without a choke inductor has an improved Power gain. Simulation results of the 2.4GHz designed LNA shows a high power gain of 21dB, a noise figure of 2.2dB, and the power consumption of 255mW at 2.5V power supply.

• The Magazine of the IEIE
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• v.41 no.8
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• pp.26-31
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• 2014

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.365-368
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• 2000

This paper describes image-rejection down conversion mixer for bluetooth application using 0.35u CMOS process. the proposed architecture is composed of LO phase shifter, mixer core, IF buffer, and IF phase shifter. IF phase shifter is designed using polyphase fillet. Simulation results show conversion gain = l0㏈, input 1㏈ compression point = -15.7㏈m. input third-order intercept point(IIP3) = -4.4㏈m, and image-rejection ratio = 37.8㏈, respectively, at 3V supply voltage, and 15.7㎃ current.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• Journal of the Korea Convergence Society
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• v.6 no.2
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• pp.65-70
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• 2015

As the new technologies like IoT and Fintech appear which have not existed before, security threat ranges in existing system are increasing. Especially, IoT has increasing ranges to cause malicious behaviors in specific systems because related IT infrastructure ranges are increasing. Fintech also requires the innovation of traditional security system because it has new structure which didn't exist in the past. As IoT and Fintech technologies are commercialized and related markets are developing in the future, structural security threats could be connected to actual attacks and secondary attacks by the attackers' imbedding of back door in IoT internet devices through remote access. Customer's device cannot be compulsively controlled for security in new system where these various security threats exist. Therefore, these services should minimize the collected information, and now is the time to politically control the utilizing methods of the collected information. In this thesis, security threats are to be suggested which could occur in newly appearing mobile services like IoT and Fintech.

• Journal of Korea Multimedia Society
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• v.6 no.2
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• pp.352-359
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• 2003

In this paper, we designed the bluetooth receiver using the microstrip bandpass filter and the high gain low noise amplifier with the 0.2$\mu\textrm{m}$ CMOS technology. A cascode inverter is adopted to implement the low noise amplifier and is one stage amplifier with a voltage reference and without the choke inductor. The designed 2.4GHz LNA was achieved a power gain of 18dB, a noise figure of 2.8dB, and the power consumption of 255mW at 2.5V power supply. Also, the microstrip receiver bandpass filter was designed that the center frequency was 2.45GHz, the bandwidth was 4% and the insert attenuation was -1.9dB. When the microstrip bandpass filter and LNA was simulated together the power gain was 16.3dB.

• Proceedings of the IEEK Conference
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• 2000.06e
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• pp.191-194
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• 2000

A 2.4 GHz single ended two stage low noise amplifier(LNA) is designed for Bluetooth application. The circuit was implemented in a standard digital 0.25 $\mu\textrm{m}$ CMOS process with one poly and five metal layers. At 2.4 GHz, the LNA dissipates 34.5 mW from a 2.5V power supply voltage and provides 24.6 dB power gain, 2.85 dB minimum noise figure, -66.3 dB reverse isolation, and an output 1-dB compression level of 8.5 dBm.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.4
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• pp.156-161
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• 2015

In this paper, a dual-polarized multi-band multi-layer antenna for a vehicle, which operates in the GPS, bluetooth, and DSRC bands, was implemented. The antenna was designed as a multi-layer structure, and a FR4-epoxy substrate with =4.4 and =1.6mm was used. GPS and DSRC antennas have circular polarized characteristics, and a single probe feeding method was applied. Simulated results by Ansys HFSS v11 was compared with the measured ones. The size of the optimally designed antenna is $67mm{\times}67mm{\times}4.8mm$, -10dB bandwidth of the anatenna was measured to be 820MHz, 127MHz, and 862MHz in each band, and 3dB AR bandwidth of the antenna was simulated to be 19MHz and 110MHz in GPS and DSRC bands. The results confirmed that suggested system satisfies the system requirements.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.260-264
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• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.463-465
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• 2015

사물인터넷 (IoT), 핀테크(Fintech) 등 새로운 기술의 등장으로 보안성에 대한 부분이 커지고 있다. 모든 사물이 인터넷과 연결되는 사물인터넷 기술로 인해 악성행위와의 접점이 크게 증가했으며, 핀테크(Fintech)는 전통적인 보안시스템의 개혁을 요구하고 있기 때문이다. 사물인터넷 환경에서 이루어지는 간편 인증 결제시스템이 발전함에 따라 다양한 보안위협요소가 발생할 것으로 예상한다. 접점의 증가로 인해 고객이 실수로 악성코드를 받게 될 가능성과 사물인터넷의 핵심 기능인 원격접속에 대한 위협이 대표적인 예라고 할 수 있다. 그러나 현재 고객의 단말을 강제로 통제할 수 있는 방법이 전무한 상황이고, 향후 서비스에서 필요한 고객정보수집과 활용에 대한 정책이 필요한 시점에서 발생할 수 있는 해킹 기법을 제안하고자 한다.