• Title/Summary/Keyword: Blocking Voltage

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Design and Fabrication of a Transient Voltage Stocking Device for Electrical Mains (전원회로용 과도전압 차단장치의 설계 및 제작)

  • 이종혁;송재용;길경석
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.11a
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    • pp.486-489
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    • 1999
  • This paper deals with the design rule and performance results of the transient voltage blocking devices (TBD) for low-voltage mains on shipboard. The proposed TBD consists of metal oxide varistors (MOV) and L-C filter to improve noise-elimination performance. Three kinds of TBDs are fabricated and tested by using a combination surge generator which can produce the standard impulse current of 8/20${\mu}$s 2.1kA. As a reults, the proposed TBD with series L-C filter has more excellent transient blocking and noise reduction performance than the conventional TBDs.

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Performance Comparison of Vertical DMOSFETs in Ga2O3 and 4H-SiC (Ga2O3와 4H-SiC Vertical DMOSFET 성능 비교)

  • Chung, Eui Suk;Kim, Young Jae;Koo, Sang-Mo
    • Journal of IKEEE
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    • v.22 no.1
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    • pp.180-184
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    • 2018
  • Gallium oxide ($Ga_2O_3$) and silicon carbide (SiC) are the material with the wide band gap ($Ga_2O_3-4.8{\sim}4.9eV$, SiC-3.3 eV). These electronic properties allow high blocking voltage. In this work, we investigated the characteristic of $Ga_2O_3$ and 4H-SiC vertical depletion-mode metal-oxide-semiconductor field-effect transistors. We demonstrated that the blocking voltage and on-resistance of vertical DMOSFET is dependent with structure. The structure of $Ga_2O_3$ and 4H-SiC vertical DMOSFET was designed by using a 2-dimensional device simulation (ATLAS, Silvaco Inc.). As a result, 4H-SiC and $Ga_2O_3$ vertical DMOSFET have similar blocking voltage ($Ga_2O_3-1380V$, SiC-1420 V) and then when gate voltage is low, $Ga_2O_3-DMOSFET$ has lower on-resistance than 4H-SiC-DMOSFET, however, when gate voltage is high, 4H-SiC-DMOSFET has lower on-resistance than $Ga_2O_3-DMOSFET$. Therefore, we concluded that the material of power device should be considered by the gate voltage.

A Comparative Study on the Various Blocking Layers for Performance Improvement of Dye-sensitized Solar Cells

  • Woo, Jong-Su;Jang, Gun-Eik
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.6
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    • pp.312-316
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    • 2013
  • In this study, short-circuit preventive layer (blocking layer) was deposited between conductive transparent electrode and porous $TiO_2$ film in the DSSCs. As blocking layer, we selected the metal-oxide such as $TiO_2$, $Nb_2O_5$ and ZnO. The sheet resistance with each different blocking layers were 18 ${\Omega}/sq.$ for the $TiO_2$, 10 ${\Omega}/sq.$ for the $Nb_2O_5$ and 8 ${\Omega}/sq.$ for the ZnO, while the RMS (Root Mean Square) roughness value of DSSCs were 39.61 nm for the $TiO_2$, 41.84 nm for the $Nb_2O_5$ and 36.14 nm for the ZnO respectively. From the results of photocurrent-voltage curves, a sputtered $Nb_2O_5$ blocking layer showed higher performance on 2.64% of photo-electrochemical properties. The maximum of conversion efficiency which was achieved under 1 sun irradiation by depositing the blocking layer increased up to 0.56%.

A Novel Multi-Level Inverter Configuration for High Voltage Conversion System

  • Suh, Bum-Seok;Lee, Yo-Han;Hyun, Dong-Seok
    • Journal of Electrical Engineering and information Science
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    • v.1 no.2
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    • pp.109-118
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    • 1996
  • This paper deals with a new multi-level high voltage source inverter with GTO Thyristors. Recently, a multi-level approach seems to be the best suited for implementing high voltage conversion systems because it leads to harmonic reduction and deals with safe high power conversion systems independent of the dynamic switching characteristics of each power semiconductor device. A conventional multi-level inverter has some problems; voltage unbalance between DC-link capacitors and larger blocking voltage across the inner switching devices. To solve these problems, the novel multi-level inverter structure is proposed.

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Study on Fabrication of The Lateral Trench Electrode IGBT with a p+ Diverter having Excellent Electrical Characteristics (우수한 전기적 특성을 갖는 p+ 다이버터를 갖는 LTEIGBT의 제작에 관한 연구)

  • 김대원;박전웅;김대종;오대석;강이구;성만영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.342-345
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    • 2002
  • A new lateral trench electrode IGBT with p+ diverter was Proposed to suppress latch-up of LTIGBT. The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEIGBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occurred at an anode current density of 540A/$\textrm{cm}^2$. And the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. That of the conventional LTIGBT of the same size was no more than 105V. When the gate voltage is applied 12V, the forward conduction currents of the Proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90mA and 70mA, respectively, at the same breakdown voltage of 150V.

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Electric Circuit Analysis for PV Array on Short-Circuit Failure of Bypass Diode in PV Module (PV모듈의 바이패스 다이오드 단락 고장 시 태양광어레이 회로 특성분석)

  • Lee, Chung-Geun;Shin, Woo-Gyun;Lim, Jong Rok;Hwang, Hye-Mi;Ju, Young-Chul;Jung, Young-Seok;Kang, Gi-Hwan;Chang, Hyo-Sik;Ko, Suk-Whan
    • Journal of the Korean Solar Energy Society
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    • v.39 no.6
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    • pp.15-25
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    • 2019
  • As the installation of photovoltaic systems increases, fire accidents of PV system grow every year. Most of PV system fires have been reported to be caused by electrical components. The majority of fire accidents occurred in combiner box, which is presumed to be short-circuit accidents due to dustproof and waterproof failures or heat deterioration of blocking diode. For this reason, the blocking diode installation became optional by revised PV combiner regulation. In this paper, according to the revised regulation, reverse current that generated by voltage mismatch was measured and analyzed in PV array without a blocking diode. The factors that cause voltage mismatch in array are assumed to be shaded PV module and short circuit failure of bypass diode. As the result of experiment, there is no reverse current to flow under shading condition in module, but reverse current flows on the failure of bypass diode in module. According to the module's I-V characteristic curve analysis, open voltage was slightly reduced due to operation of bypass diode in shading. However, it showed that open circuit voltage has decreased significantly in the failure of bypass diode. This indicates that the difference in open voltage reduction of voltage mismatch factor causes reverse current to flow.

The structural dependence of current blocking layers on the static and dynamic performances in a direct modulated semiconductor laser (반도체 레이저의 전류 차단층 구조들이 정적 및 동적특성에 미치는 영향)

  • 김동철;심종인;박문규;강중구;방동수;장동훈;어영선
    • Korean Journal of Optics and Photonics
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    • v.14 no.4
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    • pp.423-428
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    • 2003
  • In a direct modulated semiconductor laser diode. the structural dependence of current blocking layers was studied in view of the leakage current reduction and the bandwidth expansion. To analyze the leakage current and the parasitic effects, the current-voltage derivation characteristics and the subtraction method were used, respectively. It was shown that the‘inin’type current blocking structure might be the best choice for the purpose of the static and dynamic characteristics.

Feasibility of ferroelectric materials as a blocking layer in charge trap flash (CTF) memory

  • Zhang, Yong-Jie;An, Ho-Myoung;Kim, Hee-Dong;Nam, Ki-Hyun;Seo, Yu-Jeong;Kim, Tae-Geun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.119-119
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    • 2008
  • The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

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The Effect of a Sol-gel Formed TiO2 Blocking Layer on the Efficiency of Dye-sensitized Solar Cells

  • Cho, Tae-Yeon;Yoon, Soon-Gil;Sekhon, S.S.;Kang, Man-Gu;Han, Chi-Hwan
    • Bulletin of the Korean Chemical Society
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    • v.32 no.10
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    • pp.3629-3633
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    • 2011
  • The effect of a dense $TiO_2$ blocking layer prepared using the sol-gel method on the performance of dye-sensitized solar cells was studied. The blocking layer formed directly on the working electrode, separated it from the electrolyte, and prevented the back transfer of electrons from the electrode to the electrolyte. The dyesensitized solar cells were prepared with a working electrode of fluorine-doped tin oxide glass coated with a blocking layer of dense $TiO_2$, a dye-attached mesoporous $TiO_2$ film, and a nano-gel electrolyte, and a counter electrode of Pt-deposited FTO glass. The gel processing conditions and heat treatment temperature for blocking layer formation affected the morphology and performance of the cells, and their optimal values were determined. The introduction of the blocking layer increased the conversion efficiency of the cell by 7.37% for the cell without a blocking layer to 8.55% for the cell with a dense $TiO_2$ blocking layer, under standard illumination conditions. The short-circuit current density ($J_{sc}$) and open-circuit voltage ($V_{oc}$) also were increased by the addition of a dense $TiO_2$ blocking layer.

An Inherent Zero-Voltage and Zero-Current-Switching Full-Bridge Converter with No Additional Auxiliary Circuits

  • Wang, Jianhua;Ji, Baojian;Wang, Hongbo;Chen, Naifu;You, Jun
    • Journal of Power Electronics
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    • v.15 no.3
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    • pp.610-620
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    • 2015
  • An inherent zero-voltage and zero-current-switching phase-shifted full-bridge converter with reverse-blocking insulated-gate bipolar transistor (IGBT) or non-punch-through IGBT is proposed in this paper. This converter not only ensures that the switches in the lagging leg works at zero-current switching, but also minimizes circulating conduction loss without any additional auxiliary circuits. A 1.2 kW hardware prototype is designed, fabricated, and tested to verify the proposed topology. The control loop design procedures with small-signal models are also presented. A simple, low-cost, and robust democratic current-sharing circuit is also introduced and verified in this study. The proposed converter is a suitable alternative for compact, cost-effective applications with high-voltage input.