• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.844-850
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• 2002

Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.289-292
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• 2004

반도체 소자의 파괴 원인으로는 주로 열, 전압, 전류, 진동 및 압력 등이 있다. 이 중에서 전압과 열을 스트레스 인자로 적용하여 가속열화 시험을 진행하였다. 전압 및 열에 의한 소자의 열화정도를 파악하기 위해 현재 상용화되어 있는 Phase Control Thyristor 중 $V_{DRM}\;=\;1500V,\;V_{BRM}\;=\;1500V, \;T_{HS}\;=\;-40{\sim}125^{\circ}C$ 정도의 사양을 가지는 소자를 사용하였다. 열화에 의한 여러 가지 변동특성 중에서 소자의 순방향 및 역방향 항복특성의 변화와 누설전류의 변화에 대해 실험을 통해 알아보았다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.3
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• pp.183-189
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• 2010

In this paper, the trench gate emitter switched thyristor(EST) withl trench gate electrode is proposed for improving snap-back effect which leads to a lot of problems in device applications. The parasitic thyristor which is inherent in the conventional EST is completely eliminated in this structure, allowing higher maximum controllable current densities for ESTs. The dual trench gate allows homogenous current distribution in the EST and preserves the unique feature of the gate controlled current saturation of the thyristor current. The characteristics of the 1700 V forward blocking EST obtained from two-dimensional numerical simulations (MEDICI) is described and compared with that of a conventional EST. we carried out layout, design and process of EST devices.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.71-74
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• 2003

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improve the snap-back effect which leads to a lot of problem of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor(EST) with trench electrode has been proposed for improving snap-back effect. It is observed that the forward blocking voltage of the proposed device is 800V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrode, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.06a
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• pp.1035-1040
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• 2005

This paper deals with the design rule and performance results of the surge protective devices (SPDs) for low-voltage mains on shipboard. The proposed SPDs consists of a metal oxide varistors (MOV) and a L-C filter to improve noise-elimination performance. Three kinds of SPDs are fabricated and tested by using a combination surge generator which produce the standard impulse current of 8/20${\mu}s$ 2.1kA. As a results, the proposed SPDs with series L-C filter have more excellent transient blocking and noise reduction performance than the conventional ones.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.541-546
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• 1998

This paper proposes a new snubber circuit for multilevel inverter and converter. The snubber circuit makes use of Undeland snubber as basic snubber unit and can be regraded as a generalized Undeland snubber. The proposed snubber keeps such good features as fewer number of components, improved efficiency due to low loss snubber, capability of clamping overvoltage across main switching devices, and no unbalance problem of blocking voltage. Furthermore, the proposed concept of constructing a snubber circuit for multilevel inverter and converter can apply to any kind of basic snubber unit such as Holtz nondissipative snubber, McMurray efficient snubber, Lauritzen lossless snubber, etc which have been utilized for two-level inveter.

• Proceedings of the KIEE Conference
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• 2002.11b
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• pp.299-302
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• 2002

The second harmonic component is commonly used for blocking differential relay in Power transformers. However it is difficult to distinguish between inrush and internal winding fault with differential current protective relaying. This paper proposed a new method using nuro-fuzzy. The used data in nuro-fuzzy algorithm are 3-phase primary voltage and fundamental harmonic of differential current. Various states of transformer are simulated using BCTRAN and HYSDAT of EMTP. As a result of applying the algorithm in various cases, the correct discrimination between internal winding fault and inrush performed.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.938-940
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• 1999

We have fabricated SiC Schottky diode for high temperature applications. SiC thin film for drift region has been deposited by ICP-CVD. In order to establish metallization conditions, we have extracted the device parameters of the Schottky diode from the forward I-V characteristics and the C-V characteristics as a function of temperature. The ideality factor was varied from 2.07 to 1.15 and the barrier height was also varied from 1.26eV to 1.92eV with increase of temperature. The reverse blocking voltage was 183 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.136-136
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• 2011

반도체 및 전자기기 산업에 있어서 NVM은 아주 중요한 부분을 차지하고 있다. NVM은 디스플레이 분야에 많은 기여를 하고 있는데, 측히 AMOLED에 적용이 가능하여 온도에 따라 변하는 구동 전류, 휘도, color balance에 따른 문제를 해결하는데 큰 역할을 한다. 본 연구에서는 bottom gate 구조의 nc-Si NVM 실험을 진행하였다. P-type silicon substrate (0.01~0.02 ${\Omega}-cm$) 위에 Blocking layer 층인 SiO2 (SiH4:N2O=6:30)를 12.5nm증착하였고, Charge trap layer 층인 SiNx (SiH4:NH3=6:4)를 20 nm 증착하였다. 마지막으로 Tunneling layer 층인 SiOxNy은 N2O (2.5 sccm) 플라즈마 처리를 통해 2.5 nm 증착하였다. 이러한 ONO 구조층 위에 nc-Si을 50 nm 증착후에 Source와 Drain 층을 Al 120 nm로 evaporator 이용하여 증착하였다. 제작한 샘플을 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio, Programming & Erasing 특성, Charge retention 특성 등을 알아보았다.

• The Journal of Korean Medicine
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• v.21 no.1
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• pp.77-83
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• 2000

This study investigated the effects of Siegesbeckia glabrescens, an antihypertensive remedy, on the contraction evoked by phenylephrine and KCl in isolated rat thoracic arata, and also analyzed antioxidative status in vitro. Siegesbeckia glabrescens revealed dose-dependent relaxation on phenylephrine(PE)/KCl-induced arterial contraction and more markedly on PE-induced contraction. Siegesbeckia glabrescens reduced malondialdehyde(MDA)levels, Phosphatidyl choline-liposome(PC-OOH) contents, linoleic acid-induced lipid peroxidation and exerted 1,1-diphenyl-2- picryl-hydrazyl(DPPH) radical scavenging effect, in vitro. These results indicated that Siegesbeckia glabrescens doesn't relaxe artery through a blocking α-adrenergic receptor and calcium channel mediated by voltage-operated calcium channel, and it s antioxidative effects may be involved in endothelium-dependent relaxation of arteries via vascular protective properites. (J Korean Oriental Med 2000;21(1):77-83)