• Journal of the Institute of Convergence Signal Processing
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• v.22 no.3
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• pp.110-115
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• 2021

With the era of the 4th Industrial Revolution, education on artificial intelligence is one of the important topics. However, since existing education is aimed at knowledge, it is not suitable for developing the active problem-solving ability and AI utilization ability required by artificial intelligence education. To solve this problem, we proposes PBL-based education method in which learners learn in the process of solving the presented problem. The problem presented to the learner is a completed project. This project consists of three types: a classification model, the training data of the classification model, and the block code to be executed according to the classified result. The project works, but each component is designed to perform a low level of operation. In order to solve this problem, the learners can expect to improve their computational thinking skills by finding problems in the project through testing, finding solutions through discussion, and improving to a higher level of operation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• The KIPS Transactions:PartB
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• v.11B no.3
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• pp.309-316
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• 2004

In this paper, we proposed the TDS(T-shape Diamond Search) based on the directions of above, below, left and right points to estimate the motion vector fast and more correctly in this method, we exploit the facts that most motion vectors are enclosed in a circular region with a radius of 2 fixels around search center(0,0). At first, the 4 points in the above, below, left and right around the search center is calculated to decide the point of the MBD(Minimum Block Distortion). And then w. above point of the MBD is checked to calculate the SAD. If the SAD of the above point is less than the previous MBD, this process is repeated. Otherwise, the right and left points of MBD are calculated to decide The points that have the MBD between right point and left point. Above processes are repeated to the predicted direction for motion estimation. Especially, if the motions of image are concentrated in the crossing directions, the points of other directions are omitted. As a result, we can estimate motion vectors fast. Experiments show that the speedup improvement of the proposed algorithm over Diamond Search algorithm(DS) and HEXgon Based Search(HEXBS) can be up to 38∼50％ while maintaining similar image Quality.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.26-28
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• 2007

The motion estimation is the most important technique in the image compression of the video standards. In the case of next generation standards in the video codec as H.264, a high compression-efficiency can be also obtained by using a motion compensation. To obtain the accurate motion search, a motion estimation should be achieved up to 1/2 pixel and 1/4 pixel uiuts. To do this, the computational complexity is increased although the image compression rate is increased. Therefore, in this paper, we propose the advanced sub-pixel block matching algorithm to reduce the computational complexity by using a statistical characteristics of SAD(Sum of Absolute Difference). Generally, the probability of the minimum SAD values is high when searching point is in the distance 1 from the reference point. Thus, we reduced the searching area and then we can overcome the computational complexity problem. The main concept of proposed algorithm, which based on TSS(Three Step Search) method, first we find three minimum SAD points which is in integer distance unit, and then, in second step, the optimal point is in 1/2 pixel unit either between the most minimum SAD value point and the second minimum SAD point or between the most minimum SAD value point and the third minimum SAD point In third step, after finding the smallest SAD value between two SAD values on 1/2 pixel unit, the final optimized point is between the most minimum SAD value and the result value of the third step, in 1/2 pixel unit i.e., 1/4 pixel unit in totally. The conventional TSS method needs an eight.. search points in the sub-pixel steps in 1/2 pixel unit and also an eight search points in 1/4 pixel, to detect the optimal point. However, in proposed algorithm, only total five search points are needed. In the result. 23 % improvement of processing speed is obtained.

• KIPS Transactions on Software and Data Engineering
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• v.11 no.1
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• pp.29-34
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• 2022

We propose a novel network architecture and build dataset for recognizing clickable objects on mobile device screens. The data was collected based on clickable objects on the mobile device screen that have numerous resolution, and a total of 24,937 annotation data were subdivided into seven categories: text, edit text, image, button, region, status bar, and navigation bar. We use the Deconvolution Single Shot Detector as a baseline, the backbone network with Squeeze-and-Excitation blocks, the Single Shot Detector layer structure to derive inference results and the Feature pyramid networks structure. Also we efficiently extract features by changing the input resolution of the existing 1:1 ratio of the network to a 1:2 ratio similar to the mobile device screen. As a result of experimenting with the dataset we have built, the mean average precision was improved by up to 101% compared to baseline.

• Journal of Practical Engineering Education
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• v.8 no.2
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• pp.111-120
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• 2016

Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1307-1316
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• 1996

In this paper, we propose a vector quantization method which uses a dynamic address mapping based on exploring the high interblock correlation. In the proposed method, we reduce bit-rate by defining an address transform function, which maps a VQ address of an input block which will be encoded into a new address in the reordered codebook by using side match error. In one case that an original address can be transformed into a new transformed address which is lower than the threshold value, we encode the new address of the transformed convector, and in the other case we encode the address of the original convector which is not transformed. Experimental results indicate that the proposed scheme reduces the bit-rate by 45~50% compared with the ordi-nary VQ method forimage compression, at the same quality of the reconstructed image as that of the ordinary VQ system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.92-101
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• 2004

This paper proposes a algorithm to extract the variety region (object) from video for the real-time encoding of MPEG-4 based. The previous object segmentation methods cannot used the videophone or videoconference required by real-time processing. It is difficult to transfer a video to real-time because it increased complexity for the operation of each pixel on the spatial segmentation and temporal segmentation method proposed by MPEG-4 Working Group. But algorithm proposed for this thesis not operates a pixel unit but operates a macro block unit. Thus this enables real-time transfer. But this algorithm cannot extract several object for a image using proposed algorithm as previous algorithm. On system constructed by encoder and decoder. A proposed algorithm inserted for encoder as pre-process.

• Nuclear Engineering and Technology
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• v.55 no.9
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• pp.3268-3276
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• 2023

The practice of identifying the potential zones for mineral exploration in a speedy and low-cost method includes the use of satellite imagery analysis as a part of remote sensing techniques. It is challenging to explore the iron mineralization of a region through conventional methods which are a time-consuming process. The current study utilizes the Hyperion satellite imagery for mapping the iron mineralization and associated geological features in the Irikkur region, Kannur, Kerala. Along with the remote sensing results, the field study and laboratory-based analysis were conducted to retrieve the ground truth point and geochemical proportion to verify the iron ore mineralization. The MC simulation showed for shielding properties indicate an increase in the linear attenuation coefficient with raising the Fe₂O₃+SiO₂ concentrations in the investigated rocks where it is varied at 0.662 MeV in the range 0.190 cm^-1 - 0.222 cm^-1 with rising the Fe₂O₃+SiO₂ content from 57.86 wt% to 71.15 wt%. The analysis also revealed that when the γ-ray energy increased from 0.221 MeV to 2.506 MeV, sample 1 had the largest linear attenuation coefficient, ranging from 9.33 cm1 to 0.12 cm^-1. Charnockite rocks were found to have exceptional shielding qualities, making them an excellent natural choice for radiation shielding applications.