• Journal of Electrical Engineering and Technology
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• 제6권5호
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• pp.706-712
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• 2011

Necessary and sufficient conditions for the existence of diagonal, block-diagonal, and triangular decoupling controllers in linear multivariable systems for the most general setting are presented. The plant model in this study is sufficiently general to accommodate non-square plant and non-unity feedback cases with one-degree-of-freedom (1DOF) or two-degree-of-freedom (2DOF) controller configuration. The existence condition is described in terms of rank conditions on the coefficient matrices in partial fraction expansions.

• 한국전산유체공학회:학술대회논문집
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• 한국전산유체공학회 2000년도 추계 학술대회논문집
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• pp.129-134
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• 2000

An efficient numerical method to solve the unsteady incompressible Navier-Stokes equations is developed. A fully implicit time advancement is employed to avoid the CFL(Courant-Friedrichs-Lewy) restriction, where the Crank-Nicholson discretization is used for both the diffusion and convection terms. Based on a block LU decomposition, velocity-pressure decoupling is achieved in conjunction with the approximate factorization. Main emphasis is placed on the additional decoupling of the intermediate velocity components with only n th time step velocity The temporal second-order accuracy is Preserved with the approximate factorization without any modification of boundary conditions. Since the decoupled momentum equations are solved without iteration, the computational time is reduced significantly. The present decoupling method is validated by solving the turbulent minimal channel flow unit.

• 대한기계학회논문집B
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• 제24권10호
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• pp.1317-1325
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• 2000

A new efficient numerical method for computing three-dimensional, unsteady, incompressible flows is presented. To eliminate the restriction of CFL condition, a fully-implicit time advancement in which the Crank-Nicolson method is used for both the diffusion and convection terms, is adopted. Based on an approximate block LU decomposition method, the velocity -pressure decoupling is achieved. The additional decoupling of the intermediate velocity components in the convection term is made for the fully -implicit time advancement scheme. Since the iterative procedures for the momentum equations are not required, the velocity components decouplings bring forth the reduction of computational cost. The second-order accuracy in time of the present numerical algorithm is ascertained by computing decaying vortices. The present decoupling method is applied to minimal channel flow unit with DNS (Direct Numerical Simulation).

• Journal of Power Electronics
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• 제19권4호
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• pp.881-893
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• 2019

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

• 화약ㆍ발파
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• 제36권4호
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• pp.35-47
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• 2018

본 연구에서는 콘크리트 블록발파 실험과 AUTODYN 수치해석을 통해 몇 가지 전색제 및 충전재가 폭발결과에 미치는 효과를 분석하였다. 전색제와 충전재는 공기, 모래, 폴리머 겔을 이용하였다. 이들 재료들의 전색효과 및 충전효과는 밀장전 조건의 경우와 비교하였다. 매립된 콘크리트 블록을 사용하여 현장 누두공 시험을 실시하였다. 콘크리트 블록 실험 및 수치해석 결과 폴리머 겔을 사용한 경우가 모래 및 디커플링의 경우에 비해 누두공의 크기와 발파공 주위의 최대압력이 더 크게 나타나는 것을 확인하였다. 또한, 수치해석 결과는 현장시험 결과와 잘 일치하는 경향을 보여주었다. 주변암반 중에서 계산된 최대압력은 폴리머 겔, 모래, 무전색 및 디커플링 조건일 때 각각 37, 30, 16 MPa로 나타났다. 수치해석 모델 내 밀장전 시 최대 압력은 52 MPa로 가장 높게 나타났다. 그러나 손상영역의 크기는 폴리머 겔을 사용한 경우보다 작게 나타났다. 또한, 밀장전은 기준 실험으로 사용되었다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.143-146
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• 2011

본 논문은 1.2Vpp differential 입력 범위를 가지는 50-MS/s 10-hit pipelined ADC를 소개한다. 설계된 pipelined ADC는 8단의 1.5bit/stage, 1단의 2bit/stage와 digital correction 블록, bias circuit 및 reference driver, 그리고 clock generator로 구성된다. 1.5bit/stage는 sub-ADC, DAC, gain stage로 구성된다. 특히, 설계된 pipelined ADC에서는 hardware와 power consumption을 줄이기 위해 SHA를 제거하였으며, 전체 ADC의 dynamic performance를 향상시키기 위해 linearity가 개선된 bootstrapped switch를 사용하였다. Sub-ADC를 위한 reference 전압은 외부에서 인가하지 않고 on-chip reference driver에서 발생시킨다. 제안된 pipelined ADC는 1.8V supply, $0.18{\mu}m$ 1-poly 5-metal CMOS 공정에서 설계되었으며, power decoupling capacitor를 포함하여 $0.95mm^2$의 칩 면적을 가진다. 또한, 60mW의 전력소모를 가진다. 또한, Nyquist sampling rate에서 9.3-bit의 ENOB를 나타내었다.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• 한국항공우주학회지
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• 제31권3호
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• pp.39-49
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• 2003

본 논문에서는 먼저 델타연산자 접근법과 섭동기법을 소개하였다. 전자는 수치연산에 있어서 round-off error를 줄여주고 후자는 시스템을 빠른 종속시스템과 느린 종속시스템으로 분리하여 연산시간을 줄여준다. 항공기의 동력학은 종방향 혹은 횡방향 모두 장주기(Phugoid)와 단주기 운동을 동시에 보여준다. 여기서는 경비행기 Beaver의 횡방향 모델에 섬동기법과 델타접슨법을 적용하여 얻는 근사치 해를 정확한 해와 비교하였다. 그 겨로가 개루프 시스템의 경우는 단 한번의 iteration을 시행하여 얻은 근사치 해가 정확한 해와 일치했고, 페루프 시스템의 경우는 iteration없이도 근사치 값이 정확한 해와 일치하였다. 이로써 제안된 방법들의 적용이 항공기 동력학 및 제어에 있어서 매우 유효함이 검증되었다.

• 자원환경지질
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• 제25권1호
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• pp.61-72
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• 1992

단양지역은 단양탄전 서남부에 위치하며, 습곡작용과 드러스트 단층운동을 받은 중생대와 고생대 지층들로 구성되어 있다. 연구지역은 대규모의 조구조선, 동으로는 옥동단층과 서쪽에는 각동 드러스트 단층으로 경계지워져 있다. 연구지역내에 발달하고 있는 지질구조 요소들을 해석한 결과 연구지역내의 지층들이 4번에 걸쳐서 변형작용을 받았다. 옥동단층을 따라서 발달하고 있는 압쇄대는 첫번째 변형작용($D_1$) 중에 형성되었으며, 이와 관련된 구조로는 장산규암층내에 불연속적으로 발달하고 있는 압쇄대와 조서누층군내의 지층에 평행하게 발달한 인장(引長, pull-apart)구조들이 관찰된다. 두번째 변형작용중에 형성된 지질구조($D_2$)로는 북서방향의 습곡구조와 선구조들이며, 이러한 구조들은 대동 누층군 내에서는 관찰되지 않는다. 한반도 전역에 영향을 준 대보조산운동의 결과로 형성된 지질 구조들로는 ($D_3$) 각동 드러스트를 비롯한 북동방향의 드러스트 단층들과 습곡구조 등이다. 이 기간 동안에 기존의 지질구조들은 더 tight해졌으며, 변형되고 북동방향으로 회전되었다. 최후기의 변형작용($D_4$) 중에 동-서 방향의 죽령단층과 미약한 습곡구조가 형성되었다. 죽령단층내의 지층들은 주향이동 단층운동중에 회전되고 transpression의 영향을 받았다.