• Title/Summary/Keyword: Block decoupling

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Necessary and Sufficient Conditions for the Existence of Decoupling Controllers in the Generalized Plant Model

  • Park, Ki-Heon;Choi, Goon-Ho
    • Journal of Electrical Engineering and Technology
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    • v.6 no.5
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    • pp.706-712
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    • 2011
  • Necessary and sufficient conditions for the existence of diagonal, block-diagonal, and triangular decoupling controllers in linear multivariable systems for the most general setting are presented. The plant model in this study is sufficiently general to accommodate non-square plant and non-unity feedback cases with one-degree-of-freedom (1DOF) or two-degree-of-freedom (2DOF) controller configuration. The existence condition is described in terms of rank conditions on the coefficient matrices in partial fraction expansions.

An implicit velocity decoupling procedure for the incompressible Navier-Stokes equations (비압축성 Navier-Stokes 방정식에 대한 내재적 속도 분리 방법)

  • Kim KyounRyoun;Baek Seunr-Jin;Sung Hyunn Jin
    • 한국전산유체공학회:학술대회논문집
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    • 2000.10a
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    • pp.129-134
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    • 2000
  • An efficient numerical method to solve the unsteady incompressible Navier-Stokes equations is developed. A fully implicit time advancement is employed to avoid the CFL(Courant-Friedrichs-Lewy) restriction, where the Crank-Nicholson discretization is used for both the diffusion and convection terms. Based on a block LU decomposition, velocity-pressure decoupling is achieved in conjunction with the approximate factorization. Main emphasis is placed on the additional decoupling of the intermediate velocity components with only n th time step velocity The temporal second-order accuracy is Preserved with the approximate factorization without any modification of boundary conditions. Since the decoupled momentum equations are solved without iteration, the computational time is reduced significantly. The present decoupling method is validated by solving the turbulent minimal channel flow unit.

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Fully-Implicit Decoupling Method for Incompressible Navier-Stokes Equations (비압축성 나비어-스톡스 방정식의 완전 내재적 분리 방법)

  • Kim, Kyoung-Youn;Baek, Seung-Jin;Sung, Hyung-Jin
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.24 no.10
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    • pp.1317-1325
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    • 2000
  • A new efficient numerical method for computing three-dimensional, unsteady, incompressible flows is presented. To eliminate the restriction of CFL condition, a fully-implicit time advancement in which the Crank-Nicolson method is used for both the diffusion and convection terms, is adopted. Based on an approximate block LU decomposition method, the velocity -pressure decoupling is achieved. The additional decoupling of the intermediate velocity components in the convection term is made for the fully -implicit time advancement scheme. Since the iterative procedures for the momentum equations are not required, the velocity components decouplings bring forth the reduction of computational cost. The second-order accuracy in time of the present numerical algorithm is ascertained by computing decaying vortices. The present decoupling method is applied to minimal channel flow unit with DNS (Direct Numerical Simulation).

Double Boost Power-Decoupling Topology Suitable for Low-Voltage Photovoltaic Residential Applications Using Sliding-Mode Impedance-Shaping Controller

  • Tawfik, Mohamed Atef;Ahmed, Ashraf;Park, Joung-Hu
    • Journal of Power Electronics
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    • v.19 no.4
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    • pp.881-893
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    • 2019
  • This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

Power Distribution Network Modeling using Block-based Approach

  • Chew, Li Wern
    • Journal of the Microelectronics and Packaging Society
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    • v.20 no.4
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    • pp.75-79
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    • 2013
  • A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.

An Experimental and Numerical Study on the Stemming Effect of a Polymer Gel in Explosive Blasting (화약발파에서 폴리머 겔의 전색효과에 관한 실험적 및 수치해석적 연구)

  • Baluch, Khaqan;Kim, Jung-Gyu;Ko, Young-Hun;Kim, Seung-Jun;Jung, Seung-Won;Yang, Hyung-Sik;Kim, Youg-Kye;Kim, Jong-Gwan
    • Explosives and Blasting
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    • v.36 no.4
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    • pp.35-47
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    • 2018
  • In this study, several concrete-block blast tests and AUTODYN numerical analyses were conducted to analyze the effects of different stemming and coupling materials on explosion results. Air, sand, and polymer gel were used as both the stemming and coupling materials. The stemming and coupling effects of these materials were compared with those of the full-charge condition. Soil-covered or buried concrete blocks were used for field crater tests. It was found from the concrete block tests and numerical analyses that both the crater size and the peak pressure around the blast hole were higher when the polymer gel was used than when the sand and the decoupling condition were used. The numerical analyses revealed the same trend as those of the field tests. Pressure peaks in concrete block models were calculated to be 37, 30, and 16 MPa, respectively, for the cases of the polymer gel, sand, and no stemming and decoupling condition. The pressure peak was 52 MPa in the case of full-charge condition, which was the highest pressure. But the damage area for the case was smaller than that obtained from the use of polymer gel. Full-charge was also used as a reference test.

A 1.8V 50-MS/s 10-bit 0.18-um CMOS Pipelined ADC without SHA

  • Uh, Ji-Hun;Kim, Won-Myung;Kim, Sang-Hun;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.143-146
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    • 2011
  • A 50-MS/s 10-bit pipelined ADC with 1.2Vpp differential input range is proposed in this paper. The designed pipelined ADC consists of eight stage of 1.5bit/stage, one stage of 2bit/stage, digital error correction block, bias & reference driver, and clock generator. 1.5bit/stage is consists of sub-ADC, DAC and gain stage, Specially, a sample-and hold amplifier (SHA) is removed in the designed pipelined ADC to reduce the hardware and power consumption. Also, the proposed bootstrapped switch improves the Linearity of the input analog switch and the dynamic performance of the total ADC. The reference voltage was driven by using the on-chip reference driver without external reference. The proposed pipelined ADC was designed by using a 0.18um 1-poly 5-metal CMOS process with 1.8V supply. The total area including the power decoupling capacitor and power consumption are $0.95mm^2$ and 60mW, respectively. Also, the simulation result shows the ENOB of 9.3-bit at the Nyquist sampling rate.

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A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

  • Eo, Ji-Hun;Kim, Sang-Hun;Kim, Mun-Gyu;Jang, Young-Chan
    • Journal of information and communication convergence engineering
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    • v.10 no.1
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    • pp.85-90
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    • 2012
  • A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

Reduction of Computing Time in Aircraft Control by Delta Operating Singular Perturbation Technique (델타연산자 섭동방법에 의한 항공기 동력학의 연산시간 감소)

  • Sim, Gyu Hong;Sa, Wan
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.31 no.3
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    • pp.39-49
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    • 2003
  • The delta operator approach and the singular perturbation technique are introduced. The former reduces the round-off error in the numerical computation. The latter reduces computing time by decoupling the original system into the fast and slow sub-systems. The aircraft dynamics consists of the Phugoid and short-period motions whether its model is longitudinal or lateral. In this paper, an approximated solutions of lateral dynamic model of Beaver obtained by using those two methods in compared with the exact solution. For open-loop system and closed-loop system, and approximated solution gets identical to the exact solution with only one iteration and without iteration, respectively. Therefore, it is shown that implementing those approaches is very effective in the flight dynamic and control.

Structural Analysis of the Danyang Area, Danyang Coalfield, Korea (단양지역의 지질구조)

  • Kim, Jeong Hwan;Koh, Hee Jae
    • Economic and Environmental Geology
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    • v.25 no.1
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    • pp.61-72
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    • 1992
  • The Danyang area consists of the thrust and folded sedimentary rocks of Paleozoic and Mesozoic Era. The area is bounded by major tectonic units which are the Gagdong Thrust to the west and the Okdong Fault to the east. According to the structural analyses, the area is affected by polyphase deformation. This study establishes deformational sequence in the area. Mylonite zone along the Okdong Fault corresponds to the first generation of structures ($D_1$). $D_1$-structures are discrete shear zone in the Jangsan Formation and bedding parallel extensional deformation in the Cambro-Ordovician sequences. $D_2$-structures were formed prior to the sedimentation of the Jurassic Bansong Group, which are the NW-trending fold and linear structures. After sedimentation of the Bansong Group, the area is strongly affected by the Daebo Orogeny which produces NE-trending thrusts, folds and linear structures. Earlier structures were tightened and rotated toward NE. Some thrust faults did not propagate into the Bansong Group. It is suggested either the Bansong Group acted as a decoupling horizon or rest on unconformably on the thrust faults. The area is weakly affected by $D_4$-event of which structures are E-W trending folds and faults. The Jugryeong Fault clearly cut the earlier folds and thrust faults. The rocks within the fault zone were sliced and rotated during the strike-slip movements. Block rotation and transpressional features can be commonly observed.

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