• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.61.6-61
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• 2002

In these days, Block Pulse functions are used in a variety of fields such as the analysis and controller design of the systems. In applying the Block Pulse function technique to control and systems science, the integral operation of the Block Pulse series plays important roles. This is because differential equations are always involved in the representations of continuous-time models of dynamic systems, and differential operations are always approximated by the corresponding Block Pulse series through integration operational matrices. In order to apply the Block Pulse function technique to the problems of continuous-time dynamic systems more efficiently, it is necessary to find th...

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.41-49
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• 2008

This paper presents a design of the control block of a passive UHF RFID tag IC according to EPCglobal Class-1 Generation-2 UHF RFID 1.1.0 Protocol. The control block includes a PIE block, CRC5/CRC16, a Slot Counter, a Random Number Generator, a Main Control Block, a Encoder and a Memory Interface. The control block has been designed using the Verilog HDL and has been simulated. Functional simulation results for the overall control block operation show that 11 instructions with 7 states are operated correctly. Also, the control block has been implemented with 36,230 gates by Synopsys Design Compiler and Apollo using Magnachip 0.25$\mu$m technology.

• Clinics in Shoulder and Elbow
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• v.25 no.4
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• pp.339-346
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• 2022

Rotator cuff tear is the most common cause of shoulder pain in middle-age and older people. Arthroscopic rotator cuff repair (ARCR) is the most common treatment method for rotator cuff tear. Early postoperative pain after ARCR is the primary concern for surgeons and patients and can affect postoperative rehabilitation, satisfaction, recovery, and hospital day. There are numerous methods for controlling postoperative pain including patient-controlled analgesia, opioid, interscalene block, and local anesthesia. Regional blocks including interscalene nerve block, suprascapular nerve block, and axillary nerve block have been successfully and commonly used. There is no difference between interscalene brachial plexus block (ISB) and suprascapular nerve block (SSNB) in pain control and opioid consumption. However, SSNB has fewer complications and can be more easily applied than ISB. Combination of axillary nerve block with SSNB has a stronger analgesic effect than SSNB alone. These regional blocks can be helpful for postoperative pain control within 48 hours after ARCR surgery.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.5
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• pp.318-326
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• 1991

A Quantizer reconstruction level control method for block artifact reduction in DCT image coding is described. In our scheme, quantizer reconstruction level control is obtained by adding quantization level step size to the optimum quantization level in the direction of reducing the block artifact by minimizing the mean square error(MSE) and error difference(EDF) distribution in boundary without the other additional bits. In simulation results, although the performance in terms of signal to noise ratio is degraded by a little amount, mean square of error difference at block boundary and mean square error having relation block artifact is greatly reduced. Subjective image qualities are improved compared with other block artifact reduction method such as postprocessing by filtering and trasform coding by block overlapping. But the addition calculations of 1-dimensional DCT become to be more necessary to coding process for determining the reconstruction level.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.273-275
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• 2006

Ladder Diagram(LD) is the most widely utilized among many sorts of existing programs using for the design of process control system. But it is very difficult to grasp sequential flow of control logic. In this paper, we proposed the method that we can control a lot of blocks. We used PLC in process control system. And, in order to design we used Sequential Function Chart(SFC). In this paper, we proposed the method of block contro. and confirmed feasibility through a simulation.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.373-376
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• 2001

This paper has been studied a real-time video frame data processing control that used the linear systolic array for motion estimation. The proposed data control processing provides to the input data into the multiple processor array unit(MPAU) from search area and reference block data. The proposed data control architecture has based on two slice band for input data processing. And it has no required external control logic blocks for input data as like reference block or search area data.

• Journal of the Korean Data and Information Science Society
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• v.13 no.2
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• pp.175-184
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• 2002

In this paper, diallel crosses block designs for control versus test comparisons among the lines are proposed. These block designs are constructed by using partially balanced incomplete block designs with C-properties. Also, the efficiencies of the diallel crosses block designs obtained through this method are tabulated for number of lines 22 or less.

• The Korean Journal of Pain
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• v.5 no.1
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• pp.17-22
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• 1992

Splanchnic nerve block(SNP) is performed to relieve intractable upper abdominal cancer pain. Boas, in a technique using fluoroscopy, was the first to note the difference between transcrural celiac plexus block and retrocrural splanchnic nerve block(SNB). We have experienced 10 cases of SNB at the T12 level under control of fluoroscopy. Our results support this approach as an effective method for upper abdominal cancer pain control.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.8
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• pp.390-396
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• 2003

This paper is focused on an optimal block sectioning technique which are widely used in conventional railway system. We studied braking distance with pure train braking performance to generalize train braking. We tried to apply the braking distance to wayside signaling system to decide optimal block sectioning to reduce headway. The braking distances are obtained for 2 aspects, 3 aspects, 4 aspects and n aspects such that step speed control, are longer than the pure braking distance. We found an optimal solution with the generalized n aspects, and a minimum block distance for ATO mode.