• Journal of Ubiquitous Convergence Technology
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• v.2 no.1
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• pp.12-17
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• 2008

In this paper, the 128bit AES block cipher algorithm OCB (Offset Code Book) mode for privacy and authenticity of high speed packet data was efficiently designed in C language level and was optimized to support the required capacity of contents server using high performance DSP. It is known that OCB mode is about two times faster than CBC-MAC mode. As an experimental result, the encryption / decryption speed of the implemented block cipher was 308Mbps, 311 Mbps respectively at 1GHz clock speed, which is 50% faster than a general design with 3.5% more memory usage.

• Journal of Broadcast Engineering
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• v.10 no.3
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• pp.348-356
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• 2005

In this paper, we propose a fast bitrate reduction transcoding method to convert a bitstream coded by H.264 into a lower bitrate H.264 bitstream. Block mode informations and motion vectors generated by H.264 decoder are used for probability-based block mode determination in the proposed transcoding method. And the motion vector reuse and motion vector refinement process are applied in the proposed transcoding. In the experiment results, the proposed methods achieves approximately 40 times improvement in computation complexity compared with the cascaded pixel domain transcoding, while the PSNR(Peak Signal to Noise Ratio) is degraded with only $0.1\~0.3$ dB.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.255-259
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• 2008

In this paper, a current-mode integrator for low-voltage, low-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS parameter is performed and achieved 44.9dB gain, 15.7MHz unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12MHz cutoff frequency which is suitable for WCDMA baseband block.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.325-326
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• 2006

This paper proposes a new frame interpolation algorithm mainly designed for intra-mode blocks. In order to improve the accuracy of pixel interpolation, the new algorithm exploits two different interpolation modes for inter-mode blocks and intra-mode blocks, respectively. The use of the two modes reduces ghost artifacts but increases blocking artifacts between the blocks interpolated by different modes. To reduce blocking artifacts, this paper proposes an interpolation algorithm that attempts to isolate a fast moving object and interpolates such objects as the intra-mode while the remaining blocks are interpolated as the inter-mode. Simulation results show that the proposed algorithm improves subjective and objective quality of pictures by reducing ghost artifacts.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.86-92
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• 2008

Othogonal Frequency Division Multiplexing(OFDM) has been taken notice of 4th generation communication method because it has a merit of high data rate(HDR). To realize HDR communication, The OFDM a s high efficient Fast-Fourier-Transform (FFT)/Inversion FFT (IFFT) processor. Currently OFDM is realized by Digital Signal Processor(DSP) but it consumes a lot of Power. Therefore, current-mode FFT LSI has been proposed for compensation of this demerit. In this paper, we propose IVC for current-mode FFT LSI. From the simulation result, the output value of IVC is more than 3V when the value of FFT Block output is more than $7.35{\mu}A$. The output value of IVC is lower than 0.5V when the value of FFT Block output is lower than $0.97{\mu}A$. Designed IVC Low-power Current mode FFT LSI will contribute to the operation of current-mode FFT LSI and the development of next generation wireless communication systems.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.4
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• pp.262-266
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• 2011

In high data-rate communication systems, encryption/decryption must be processed in high speed. In this paper, we implement CCM security mode which is the basis of security. Specifically, we combine CCM with AES block encryption algorithm in hardware. With the combination, we can carry out encryption/decryption as well as data transmission/reception simultaneously without reducing data-rate, and we keep low-power consumption with high speed by optimizing CCM block.

• ETRI Journal
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• v.30 no.4
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• pp.506-515
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• 2008

The H.264/AVC standard has adopted new coding tools such as intra-prediction, variable block size, motion estimation with quarter-pixel-accuracy, loop filter, and so on. The adoption of these tools enables an H.264/AVC-coded bitstream to have more information than was possible with previous standards. In this paper, we propose an effective spatial error concealment method with low complexity in H.264/AVC intra-frame. From information included in an H.264/AVC-coded bitstream, we use prediction modes of intra-blocks to recover a damaged block. This is because the prediction direction in each prediction mode is highly correlated to the edge direction. We first estimate the edge direction of a damaged block using the prediction modes of the intra-blocks adjacent to a damaged block and classify the area inside the damaged block into edge and flat areas. Our method then recovers pixel values in the edge area using edge-directed interpolation, and recovers pixel values in the flat area using weighted interpolation. Simulation results show that the proposed method yields better video quality than conventional approaches.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.20-22
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• 2007

The H.264/AVC standard developed by the joint Video Team (JVT) provides better coding efficiency than previous standards. The new emerging H.264/AVC employs variable block size motion estimation using multiple reference frame with 1/4-pel MV(Motion Vector) accuracy. These techniques are a important feature to accomplish higher coding efficiency. However, these techniques are increased overall computational complexity. To overcome this problem, this paper proposes advanced fast mode decision suited for variable block size by classifying inter mode based on Rate Distortion Optimization(RDO) technique. Proposed algorithm is going to use to implement H/W structure for fast mode decision. The experimental results shows that the proposed algorithm provides significant reduction computational complexity without any noticeable coding loss and additional computation. Entire computational complexity is decreased about 30%.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.124-130
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• 2015

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast and ultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the common logics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused by the extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT are increases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can be up to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFID tag the size of circuit is less than 5,000 gates.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.601-604
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• 1999

We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Since the memory bank of the proposed architecture provides scheduled data flow for calculating 8$\times$8 block-based sum of absolute difference (SAD), both a macroblock-based motion vector (MV) and four block-based MVs are simultaneously obtained for each macroblock in the advanced prediction mode. The proposed motion estimator gives similar coding performance compared with full search block matching algorithm (FSBMA) while achieving small size and satisfying the advanced prediction mode.