• The KIPS Transactions:PartB
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• v.13B no.6 s.109
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• pp.607-614
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• 2006

In this paper, we propose an error resilience video coder which uses a hybrid error concealment algorithm. Firstly, the algorithm uses the error concealment with data hiding. If the hiding information is lost, the motion vector of lost macroblock is computed with adaptive selection of adjacent motion vectors and OBMC (Overlapped Block Motion Compensation) is applied with this motion vector. We know our algorithm is more effective in case of continuous GOB. The results show more significant improvement than many temporal concealment methods such as MVRI (Motion Vector Rational Interpolation) or existing error concealment using data hiding.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3C
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• pp.257-263
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• 2003

Error control and concealment in video communication is becoming increasingly important because transmission errors can cause single or multiple loss of macroblocks in video delivery over unreliable channels such as wireless networks and the internet. This paper describes a temporal error concealment by postprocessing. Lost image blocks are overlapped block motion compensated (OBMC) using median of motion vectors from adjacent blocks at the decoder. The results show a significant improvement over zero motion error concealment and other temporal concealment methods such as Motion Vector Rational Interpolation or Side Match Criterion OBMC by 1.4 to 3.5㏈ gain in PSNR. We present experimental results showing improvements in PSNR and computational complexity.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.6
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• pp.736-745
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• 2002

In network delivery of compressed video, packets may be lost if the channel is unreliable like Internet. Such losses tend to of cur in burst like continuous bit-stream error. In this paper, we propose an effective error-concealment approach to which an error resilient video encoding approach is applied against burst errors and which reduces a complexity of error concealment at the decoder using data hiding. To improve the performance of error concealment, a temporal and spatial error resilient video encoding approach at encoder is developed to be robust against burst errors. For spatial area of error concealment, block shuffling scheme is introduced to isolate erroneous blocks caused by packet losses. For temporal area of error concealment, we embed parity bits in content data for motion vectors between intra frames or continuous inter frames and recovery loss packet with it at decoder after transmission While error concealment is performed on error blocks of video data at decoder, it is computationally costly to interpolate error video block using neighboring information. So, in this paper, a set of feature are extracted at the encoder and embedded imperceptibly into the original media. If some part of the media data is damaged during transmission, the embedded features can be extracted and used for recovery of lost data with bi-direction interpolation. The use of data hiding leads to reduced complexity at the decoder. Experimental results suggest that our approach can achieve a reasonable quality for packet loss up to 30% over a wide range of video materials.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.108-115
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• 2009

In this paper, we propose a novel true-motion estimation technique supporting efficient frame error concealment for error-resilient video coding. In general, it is important to accurately obtain the true-motion of objects in video sequences for effectively recovering the corrupted frame due to transmission errors. However, the conventional motion estimation (ME) technique, which minimizes a sum of absolute different (SAD) between pixels of the current block and the motion-compensated block, does not always reflect the true-movement of objects. To solve this problem, we introduce a new metric called an absolute difference of motion vectors (ADMV) which is the distance between motion vectors of the current block and its motion-compensated block. The proposed ME method can prevent unreliable motion vectors by minimizing the weighted combination of SAD and ADMV. In addition, the proposed ME method can significantly improve the performance of error concealment at the decoder since error concealment using the ADMV can effectively recover the missing motion vector without any information of the lost frame. Experimental results show that the proposed method provides similar coding efficiency to the conventional ME method and outperforms the existing error-resilient method.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.721-728
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• 2018

This paper introduces various linear block error correction code and compares performances of the correction circuits. As the risk of errors due to power noise has increased, ECC(: Error Correction Code) has been introduced to prevent the bit error. There are two representatives of ECC structures which are SEC-DED(: Single Error Correction Double Error Detection) and SEC-DED-DAEC(: Double Adjacent Error Correction). According to simulation results, the SEC-DED circuit has advantages of small area and short delay time compared to SEC-DED-DAEC circuits. In case of SED-DED-DAEC, there is no big difference between Dutta's and Pedro's from performance point of view. Therefore, Pedro's code is more efficient than Dutta' code since the correction rate of Pedro's code is higher than that of Dutta's code.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2A
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• pp.99-108
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• 2002

In this paper, we discuss the effect of imperfect knowledge of the transmission channel on the M-QAM SER performance of space-time block codes. Because the channel knowledge is used for decoding of space-time block codes, the imperfect channel knowledge can degrade the performance of space-time block codes. In this paper, the channel mismatch error is modeled as errors in the estimation of the channel due to noise and errors due to the variation of the channel. We derive the analytic expression for the symbol error rate (SER) as a function of the average signal to interference ratio (SIR) per channel including the terms of channel mismatch errors. Simulation results show that the acceptable levels of channel estimation error is 10$\^$-3/ and that of channel variation is f$\_$d/T$\_$B/=0.001 at SNR=20dB in space-time block codes.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.949-955
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• 2005

In this Paper, we propose fast block matching algorithm by dividing complex areas based on complexity order of reference block and square sub-block to reduce an amount of computation of full starch(FS) algorithm for fast motion estimation, while keeping the same prediction quality compared with the full search algorithm. By using the fact that matching error is proportional to the gradient of reference block, we reduced unnecessary computations with square sub-block adaptive matching scan based image complexity instead of conventional sequential matching scan and row/column based matching scan. Our algorithm reduces about $30\%$ of computations for block matching error compared with the conventional partial distortion elimination(PDE) algorithm without any prediction quality, and our algorithm will be useful in real-time video coding applications using MPEG-4 AVC or MPEG-2.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.