• Title/Summary/Keyword: Block Cryptographic Algorithm

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A Study on Image Integrity Verification Based on RSA and Hash Function (RSA와 해시 함수 기반 이미지 무결성 검증에 관한 연구)

  • Woo, Chan-Il;Goo, Eun-Hee
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.21 no.11
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    • pp.878-883
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    • 2020
  • Cryptographic algorithms are used to prevent the illegal manipulation of data. They are divided into public-key cryptosystems and symmetric-key cryptosystems. Public-key cryptosystems require considerable time for encryption and decryption compared to symmetric-key cryptosystem. On the other hand, key management, and delivery are easier for public-key cryptosystems than symmetric-key cryptosystems because different keys are used for encryption and decryption. Furthermore, hash functions are being used very effectively to verify the integrity of the digital content, as they always generate output with a fixed size using the data of various sizes as input. This paper proposes a method using RSA public-key cryptography and a hash function to determine if a digital image is deformed or not and to detect the manipulated location. In the proposed method, the entire image is divided into several blocks, 64×64 in size. The watermark is then allocated to each block to verify the deformation of the data. When deformation occurs, the manipulated pixel will be divided into smaller 4×4 sub-blocks, and each block will have a watermark to detect the location. The safety of the proposed method depends on the security of the cryptographic algorithm and the hash function.

Area Efficient Implementation of 32-bit Architecture of ARIA Block Cipher Using Light Weight Diffusion Layer (경량화된 확산계층을 이용한 32-비트 구조의 소형 ARIA 연산기 구현)

  • Ryu, Gwon-Ho;Koo, Bon-Seok;Yang, Sang-Woon;Chang, Tae-Joo
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.6
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    • pp.15-24
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    • 2006
  • Recently, the importance of the area efficient implementation of cryptographic algorithm for the portable device is increasing. Previous ARIA(Academy, Research Institute, Agency) implementation styles that usually concentrate upon speed, we not suitable for mobile devices in area and power aspects. Thus in this paper, we present an area efficient AR processor which use 32-bit architecture. Using new implementation technique of diffusion layer, the proposed processor has 11301 gates chip area. For 128-bit master key, the ARIA processor needs 87 clock cycles to generate initial round keys, n8 clock cycles to encrypt, and 256 clock cycles to decrypt a 128-bit block of data. Also the processor supports 192-bit and 256-bit master keys. These performances are 7% in area and 13% in speed improved results from previous cases.

90/150 RCA Corresponding to Maximum Weight Polynomial with degree 2n (2n 차 최대무게 다항식에 대응하는 90/150 RCA)

  • Choi, Un-Sook;Cho, Sung-Jin
    • The Journal of the Korea institute of electronic communication sciences
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    • v.13 no.4
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    • pp.819-826
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    • 2018
  • The generalized Hamming weight is one of the important parameters of the linear code. It determines the performance of the code when the linear codes are applied to a cryptographic system. In addition, when the block code is decoded by soft decision using the lattice diagram, it becomes a measure for evaluating the state complexity required for the implementation. In particular, a bit-parallel multiplier on finite fields based on trinomials have been studied. Cellular automata(CA) has superior randomness over LFSR due to its ability to update its state simultaneously by local interaction. In this paper, we deal with the efficient synthesis of the pseudo random number generator, which is one of the important factors in the design of effective cryptosystem. We analyze the property of the characteristic polynomial of the simple 90/150 transition rule block, and propose a synthesis algorithm of the reversible 90/150 CA corresponding to the trinomials $x^2^n+x^{2^n-1}+1$($n{\geq}2$) and the 90/150 reversible CA(RCA) corresponding to the maximum weight polynomial with $2^n$ degree by using this rule block.

Gate-Level Conversion Methods between Boolean and Arithmetic Masks (불 마스크와 산술 마스크에 대한 게이트 레벨 변환기법)

  • Baek, Yoo-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.8-15
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    • 2009
  • Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

Analysis of Grover Attack Cost and Post-Quantum Security Strength Evaluation for Lightweight Cipher SPARKLE SCHWAEMM (경량암호 SPARKLE SCHWAEMM에 대한 Grover 공격 비용 분석 및 양자 후 보안 강도 평가)

  • Yang, Yu Jin;Jang, Kyung Bae;Kim, Hyun Ji;Song, Gyung Ju;Lim, Se Jin;Seo, Hwa Jeong
    • KIPS Transactions on Computer and Communication Systems
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    • v.11 no.12
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    • pp.453-460
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    • 2022
  • As high-performance quantum computers are expected to be developed, studies are being actively conducted to build a post-quantum security system that is safe from potential quantum computer attacks. When the Grover's algorithm, a representative quantum algorithm, is used to search for a secret key in a symmetric key cryptography, there may be a safety problem in that the security strength of the cipher is reduced to the square root. NIST presents the post-quantum security strength estimated based on the cost of the Grover's algorithm required for an attack of the cryptographic algorithm as a post-quantum security requirement for symmetric key cryptography. The estimated cost of Grover's algorithm for the attack of symmetric key cryptography is determined by the quantum circuit complexity of the corresponding encryption algorithm. In this paper, the quantum circuit of the SCHWAEMM algorithm, AEAD family of SPARKLE, which was a finalist in NIST's lightweight cryptography competition, is efficiently implemented, and the quantum cost to apply the Grover's algorithm is analyzed. At this time, the cost according to the CDKM ripple-carry adder and the unbounded Fan-Out adder is compared together. Finally, we evaluate the post-quantum security strength of the lightweight cryptography SPARKLE SCHWAEMM algorithm based on the analyzed cost and NIST's post-quantum security requirements. A quantum programming tool, ProjectQ, is used to implement the quantum circuit and analyze its cost.

Design and Implementation of ARIA Cryptic Algorithm (ARIA 암호 알고리듬의 하드웨어 설계 및 구현)

  • Park Jinsub;Yun Yeonsang;Kim Young-Dae;Yang Sangwoon;Chang Taejoo;You Younggap
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.4 s.334
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    • pp.29-36
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    • 2005
  • This paper presents the first hardware design of ARIA that KSA(Korea Standards Association) decided as the block encryption standard at Dec. 2004. The ARIA cryptographic algorithm has an efficient involution SPN (Substitution Permutation Network) and is immune to known attacks. The proposed ARIA design based on 1 cycle/round include a dual port ROM to reduce a size of circuit md a high speed round key generator with barrel rotator. ARIA design proposed is implemented with Xilinx VirtexE-1600 FPGA. Throughput is 437 Mbps using 1,491 slices and 16 RAM blocks. To demonstrate the ARIA system operation, we developed a security system cyphering video data of communication though Internet. ARIA addresses applications with high-throughput like data storage and internet security protocol (IPSec and TLS) as well as IC cards.

Design of Partitioned $AB^2$ Systolic Modular Multiplier (분할된 $AB^2$ 시스톨릭 모듈러 곱셈기 설계)

  • Lee, Jin-Ho;Kim, Hyun-Sung
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.1C
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    • pp.87-92
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    • 2006
  • An $AB^2$ modular operation is an efficient basic operation for the public key cryptosystems and various systolic architectures for $AB^2$ modular operation have been proposed. However, these architectures have a shortcoming for cryptographic applications due to their high area complexity. Accordingly, this paper presents an partitioned $AB^2$ systolic modular multiplier over GF($2^m$). A dependency graph from the MSB $AB^2$ modular multiplication algorithm is partitioned into 1/3 to get an partitioned $AB^2$ systolic multiplier. The multiplier reduces the area complexity about 2/3 compared with the previous multiplier. The multiplier could be used as a basic building block to implement the modular exponentiation for the public key cryptosystems based on smartcard which has a restricted hardware requirements.

An Improved Round Reduction Attack on Triple DES Using Fault Injection in Loop Statement (반복문 오류 주입을 이용한 개선된 Triple DES 라운드 축소 공격)

  • Choi, Doo-Sik;Oh, Doo-Hwan;Park, Jeong-Soo;Ha, Jae-Cheol
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.22 no.4
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    • pp.709-717
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    • 2012
  • The round reduction on block cipher is a fault injection attack in which an attacker inserts temporary errors in cryptographic devices and extracts a secret key by reducing the number of operational round. In this paper, we proposed an improved round reduction method to retrieve master keys by injecting a fault during operation of loop statement in the Triple DES. Using laser fault injection experiment, we also verified that the proposed attack could be applied to a pure microprocessor ATmega 128 chip in which the Triple DES algorithm was implemented. Compared with previous attack method which is required 9 faulty-correct cipher text pairs and some exhaustive searches, the proposed one could extract three 56-bit secret keys with just 5 faulty cipher texts.