• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.413-420
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• 2006

In this thesis, a RFID baseband system is implemented based on the international standard ISO/IEC 18000-6 Type-B using FPCA, and also anti-collision algorithm is implemented to improve the system performance. We compares the performance of the proposed anti-collision algorithm with that binary tree algorithm and bit-by-bit algorithm, and also validated analytic results using OPNET simulation. The proposed algorithm for Type-B transmission protocol and collision prohibition was designed using ISE7.1i which is a FPGA design-tool of Xilinx and implemented with Spartan2 chip which is a FPGA device.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.43-51
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• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• 전자공학회논문지 IE
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• v.43 no.4
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• pp.115-121
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• 2006

In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4A
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• pp.431-439
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• 2006

RFID Anti-Collision technique is needed to avoid collision problem caused by Radio interference between tags in the same RFID Reader area. It affects the performance and reliability of the RFID System. This paper propose the QT-CBP(Query Tree with Collision-Bit Positioning) Algorithm based on the QT(Query Tree) algorithm. QT-CBP Algorithm use precise collision bit position to improve the performance. We demonstrated the proposed algorithm by simulation. Our algorithm outperformed when each tag bit streams are the more duplicate and the number of tags is increased, compared with QT.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.107-115
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• 2014

The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.75-78
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• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.74-84
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• 2003

Conventional test algorithms do not effectively detect faults by word-line and bit-line coupling noise resulting from the increase of the density of memories. In this paper, the possibility of faults caused by word-line coupling noise is shown, and new fault model, WLSFs(Word-Line Sensitive Fault) is proposed. We also introduce the algorithm considering both word-line and bit-line coupling noise simultaneously. The algorithm increases probability of faults which means improved fault coverage and more effective test algorithm, compared to conventional ones. The proposed algorithm can also cover conventional basic faults which are stuck-at faults, transition faults and coupling faults within a five-cell physical neighborhood.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1487-1504
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• 1997

In this paper, the two-stage variable block-size multiresolution motion algorithm is proposed for an interframe coding scheme in the wavelet decomposition. An optimal bit allocagion between motion vectors and the prediction error in sense of minimizing the total bit rate is obtained by the proposed algorithm. The proposed algorithm consists of two stages for motion estimatation and only the first stage can be separated and run on its own. The first stage of the algorithm introduces a new method to give the lower bit rate of the displaced frame difference as well as a smooth motion field. In the second stage of the algorithm, the technique is introduced to have more accurate motion vectors in detailed areas, and to decrease the number of motion vectors in uniform areas. The algorithm aims at minimizin gthe total bit rate which is sum of the motion vectors and the displaced frame difference. The optimal bit allocation between motion vectors and displaced frame difference is accomplished by reducing the number of motion vectors in uniform areas and it is based on a botom-up construction of a quadtree. An entropy criterion aims at the control of merge operation. Simulation resuls show that the algorithm lends itself to the wavelet based image sequence coding and outperforms the conventional scheme by up to the maximum 0.28 bpp.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.8
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• pp.17-22
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• 2007

In this paper, we propose a threshold estimation algorithm for a noncoherent IR-UWB receiver using 1-bit sampler. The proposed method reduces the hardware complexity by using the information of binary data resulted from 1-bit sampler instead of measuring the energy level of a received signal. Besides, mathematical modeling shows that the performances are similar to those of theoretically optimal threshold in terms of bit error rate. Computer simulations based on the IEEE 802.15.4a channel model also demonstrate the superiority of the proposed algorithm.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.372-375
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• 1999

This paper proposes a bit allocation algorithm using adaptive bandwidth for ADSL that uses the DMT technology. In certain cases for high attenuation loops the conventional algorithms are unable to assign data bits to the higher frequency tones, due to the power spectrum mask limitation recommended by ANSI Standard, even if the total power budget is not expended. In the proposed bit allocation algorithm, adjacent empty tones that would not be used merge into single tone, then additional bits is assigned to the merged empty tones. Because additional bits is allocated, most of the available power is used. The proposed algorithm show that total bit increase in about 2~9% bits more than about conventional "water-filling" and "bit removal" algorithms and that is able to use about 93% of the available budget Power