• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.355-361
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• 2009

This paper proposes a new basic unit level rate control algorithm which generates the output bits corresponding to the target bits. The H.264 standard uses various coding modes and optimization methods to improve the compression performance, which makes it difficult to control the generated traffic accurately. In the proposed scheme, the allocated bits to a frame are distributed to all basic units properly to encode each basic unit according to the bit budget. After encoding the frame, the encoding parameters are adjusted according to the difference between the target and the resulting values. It is shown by experimental results that the new algorithm can generate output bit rates accurately corresponding to the target bit rates with the PSNR performance better than that of the existing rate control algorithm.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.37-44
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• 2002

This paper proposes efficient digital hardware design method by using fixed weight of pre-trained neural network. For this, arithmetic operations of PEs(Processing Elements) are represented with matrix-vector multiplication. The relationship of fixed weight and input data present bit-level array structure architecture which is consisted operation node. To minimize the operation node, this paper proposes node elimination method and setting common node depend on bit pattern of weight. The result of FPGA simulation shows the efficiency on hardware cost and operation speed with full precision. And proposed design method makes possibility that many PEs are implemented to on-chip.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.175-184
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• 2009

The distance of sensor nodes is an important factor in having influence on capability of networks in underwater acoustic sensor networks. Our proposed scheme is to establish an efficient distance to design a route of communication in underwater environment and it proposes a Level scheme that the areas divided by transmit/receive distance in network are given different levels. Our proposed scheme is pursued research to maintain a established route and maximize an energy efficiency. The established route will have fluid modification by an internal and external factors and it will construct more robust underwater sensor networks over our proposed multiple path configuration scheme.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.8
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• pp.327-336
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• 2007

Lots of effort toward design optimizations have been paid for a cost-effective system design in various ways from a transistor level to RTL designs. In this paper, we propose a bit level optimization of an adder design for expanding its design space. For the bit-level optimization, a heterogeneous adder organization utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Then, we develop an optimization method based on Integer Linear Programming to search the expanded design space of the heterogeneous adder. The novelty of the Proposed architecture and optimization method is introducing a bit level reconstruction/recombination of IPs which have same functionality but different speed and area characteristics for producing more find-grained delay-area optimization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.7C
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• pp.618-627
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• 2010

In this paper, we propose an adaptive K-best algorithm in which the number K of candidates is changed according to the differences of level radii. We also compare the bit error performance and complexity of the proposed algorithm with those of several conventional K-best algorithms, where the complexity is defined as the total number of candidates of which partial Euclidean distances have to be calculated. The proposed algorithm adaptively decides K at each level by eliminating the symbols, whose differences of radii are larger than a threshold, from the set of candidates, and the maximum or average value of differences can be adopted as the threshold. The proposed decoding algorithm shows the better bit error performance and the lower complexity than a conventional K-best decoding algorithm with a constant K, and also has a similar bit error performance and the lower complexity than other adaptive K-best algorithms.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.60-67
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• 2008

An all-optical 4-bit Gray code to binary coded decimal (BCD) converter by means of commercially available numerical analysis tool (VPI) was demonstrated, for the first time to our knowledge. Circuit design approach was modified appropriately in order to fit the electrical method on an all-optical logic circuit based on a cross gain modulation (XGM) process so that signal degradation due to the non-ideal optical logic gates can be minimized. Without regenerations, Q-factor of around 4 was obtained for the most severely degraded output bit (least significant bit-LSB) with 2.5 Gbps clean input signals having 20 dB extinction ratio. While modifying the two-level simplification method and Karnaugh map method to design a Gray code to BCD converter, a general design concept was also founded (one-level simplification) in this research, not only for the Gray code to BCD converter but also for any general applications.

• Journal of the Korean Institute of Intelligent Systems
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• v.2 no.2
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• pp.42-60
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• 1992

An adaptive fuzzy system can efficiently classify subimages into four categories according to image activity level for image data compression. The system estimates fuzzy rules by clustering input-output data generated from a given adaptive transform image coding process. The system encodes different images without modification and reduces side information when encoding multiple images. In the second part, a fuzzy system estimates optimal bit maps for the four subimage classes in noisy channels assuming a Gauss-Markov image model. The fuzzy systems respectively estimate the sampled subimage classification and the bit-allocation processes without a mathematical model of how outputs depend on inputs and without rules articulated by experts.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.239-243
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• 1989

This paper represents the control software development for Direct Drive Arm Robot with the WHILE language composed the 68000 assembly language and high level language modula-2. Direct Drive Ann Robot needs the control program which is fast step and exactly position moving because Direct Drive Arm Robt depends on accuracy. We found that the self-tuning algorithm for this robot control is very good for the real time control and the floating point operation using the 32 bit CPU(MC 68020) controller.