• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.3
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• pp.359-370
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• 2013

Lin and Chan proposed a reversible secret image sharing scheme in 2010. The advantages of their scheme are as follows: the low distortion ratio, high embedding capacity of shadow images and usage of the reversible. However, their scheme has some problems. First, the number of participants is limited because of modulus prime number m. Second, the overflow can be occurred by additional operations (quantized value and the result value of polynomial) in the secret sharing procedure. Finally, if the coefficient of (t-1)th degree polynomial become zero, (t-1) participants can access secret data. In this paper, an improved reversible secret image sharing scheme which solves the problems of Lin and Chan's scheme while provides the low distortion ratio and high embedding capacity is proposed. The proposed scheme solves the problems that are a limit of a total number of participants, and occurrence of overflow by new polynomial operation over GF($2^8$). Also, it solve problem that the coefficient of (t-1)th degree polynomial become zero by fixed MSB 4-bit constant. In the experimental results, PSNR of their scheme is decreased with the increase of embedding capacity. However, even if the embedding capacity increase, PSNR value of about 45dB or more is maintained uniformly in the proposed scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.48-58
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• 2006

This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.105-113
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• 2013

RAID systems have been widely used by connecting several disks in parallel structure. to resolve the delay and bottleneck of data I/O. Recently, SSD based RAID systems are emerging since SSDs have better I/O performance than HDD. However, endurance and power consumption problems due to frequent write operation in SSD based RAID system should be resolved. In this paper, we propose a de-duplication method of parity disk in SSD based RAID system with expensive update cost. The proposed method segments chunk of parity data into small pieces and removes duplicate data, therefore, it can reduce wear-leveling and power consumption by decreasing write operation for duplicated parity data. Experimental results show that bit update rate of the proposed method is 16% in total disk, 31% in parity disk less than that of existing method in RAID-6 system using EVENODD erasure code, and the power consumption of the proposed method is 30% less than that of existing method. Besides the proposed method is 12% in total disk, 32% in parity disk less than that of existing method in RAID-5 system, and the power consumption of the proposed method is 36% less than that of existing method.

• 전자공학회논문지 IE
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• v.46 no.4
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• pp.1-7
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• 2009

The final goal of ITS and ETC will be to improve the traffic efficiency and mobile safety without new road construction. DSRC system is emerging nowadays as a solution of them. China DSRC standard which was released in May 2007 has low bit rate, short message and simple MAC control. The DSRC system users want a long lifetime over 1 year with just one battery. In this paper, we propose the SoC of very low power consumption architecture. Several digital logic concept and analog power control logics were used for very low power consumption. The SoC operation mode and clock speed, operation voltage range, wakeup signal detector, analog comparator and Internal Voltage Regulator & External Power Switch were designed. We confirmed that the SoC power consumption is under 8.5mA@20Mhz, 0.9mA@1Mhz in active mode, and under 5uA in power down mode, by computer simulation. The design of SoC was finished on Aug. 2008, and fabricated on Nov. 2008 with $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.9
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• pp.22-30
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• 2011

Recently, the rising demand for intelligent video surveillance system leads to high-performance face recognition systems. The solution for low-resolution images acquired by a long-distance camera is required to overcome the distance limits of the existing face recognition systems. For that reason, this paper proposes a hardware design of an image resolution enhancement algorithm for real-time intelligent video surveillance systems. The algorithm is synthesizing a high-resolution face image from an input low-resolution image, with the help of a large collection of other high-resolution face images, called training set. When we checked the performance of the algorithm at 32bit RISC micro-processor, the entire operation took about 25 sec, which is inappropriate for real-time target applications. Based on the result, we implemented the hardware module and verified it using Xilinx Virtex-4 and ARM9-based embedded processor(S3C2440A). The designed hardware can complete the whole operation within 33 msec, so it can deal with 30 frames per second. We expect that the proposed hardware could be one of the solutions not only for real-time processing at the embedded environment, but also for an easy integration with existing face recognition system.

• Journal of Korea Multimedia Society
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• v.16 no.5
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• pp.577-590
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• 2013

Shamir's (k,n)-threshold secret sharing scheme is not secure against cheating by attacker because the signature of participants is omitted. To prevent cheating, many schemes have been proposed, and a proactive secret sharing is one of those. The proactive secret sharing is a method to update shares in the secret sharing scheme at irregular intervals. In this paper, a proactive image secret sharing scheme over $GF(2^8)$ is proposed for the first time. For the past 30 years, Galois field operation is widely used in order to perform the efficient and secure bit operation in cryptography, and the proposed scheme with update phase of shadow image over $GF(2^8)$) at irregular intervals provides the lossless and non-compromising of secret image. To evaluate security and efficiency of images (i.e. cover and shadow images) distortion between the proposed scheme and the previous schemes, embedding capacity and PSNR are compared in experiments. The experimental results show that the performances of the embedding capacity and image distortion ratio of the proposed scheme are superior to the previous schemes.

• The Korean Journal of Financial Management
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• v.26 no.3
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• pp.171-198
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• 2009

The primary purpose of this study is to examine the impact of new BIS regulation, which is the preparations to incorporate not only credit risk but also market and operation risk, on the bank behaviors. As methodology, SUR(seemingly unrelated regression) and pool unit test are used in the empirical analysis of banks survived in Korea. It is employed that quarterly data of BIS capital ratio, ratio of standard and below loans to total loans, ratio of liquid assets to liquid liabilities, allowances for credit losses, real GDP, yields of corporate bonds(3years, AA) covering the period of 2000Q1~2009Q1. As a result, it could be indicated that effectiveness and promoting improvements of BIS capital regulation policy as follows; First, it is explicitly seen that weight of lending had decreased and specific gravity of international investment had increased until before BIS regulation is built up a step for revised agreement in late 2001. Second, after more strengthening of BIS standard in late 2002, banks had a tendency to decrease the adjustment of assets weighted risk through issuing of national loan that is comparatively low profitability. Also, it is implicitly sought that BIS regulation is a bit of a factor to bring about credit crunch and then has become a bit of a factor of economic stagnation. Third, as the BIS regulation became hard, it let have a effort to raise the soundness of a credit loan because of selecting good debtor based on its credit ratings. Fourth, it should be arranged that the market disciplines, the effective superintendence system and the sound environment to be able to raise enormous bank capital easily, against the credit stringency and reinforce the soundness of banks etc. in Korea capital market.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1919-1927
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• 1993

A new MAC protocol has been proposed and analysed to relieve the unfairness problems exhibited by the basic version of the DQDB standard. DQDB MAC protocol has the unfairness problems in throughputs. message delay and so or. And when the slots are reused or the file transmissions takes long, the unfairness problems in the system become worse. The new access protocol proposed here, which of called the Balanced DQDB, guarantees a fair bandwidth distribution by using one bit of the dual bus network protocol and keeps up all characteristics of DQDB. the DQDB analysis model introduced by Wen Jing, et al, was considered to analyse a sequential balance distribution of solts. And the probabilities of the empty in operation mode were represented to determine the probabilities for busy bits to generate on each node of the bus using the Markov chain. Through the simulations. the performances of the proposed Balanced DQDB and that of the standard DQDB of the BWB mechanism were compared at the state that the values of the RQ or CD counter on each node varied dynamically. As the results, it is shown that the Balanced DQDB has the decrement of throughputs in upstream, but the numbers of the used empty slots at each node of the Balanced DQDB had more than that of the others because the Balanced DQDB has over 0.9 throughputs in the 70~80% nodes of total node and it has constant throughputs at each node. And there results were analogous to that of the analytical model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.2C
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• pp.160-169
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• 2002

An ATM-PON (Passive Optical Network) system consists of an OLT (Optical Line Termination), multiple ONUs (Optical Network Units) and the optical fiber which has a PON (Passive Optical Network)configuration with a passive optical splitter. To avoid cell collisions on the upstream transmission, an elaborate procedure called as ranging is needed when a new ONU is installed. The ONU can send upstream cells according to the grant provided by the OLT after the procedure. To prevent collisions being generated by the variation of several factors, OLT must performs continuously the cell phase monitoring. It means that the OLT predicts the expected arrival time, monitors the actual arrival time for all upstream cells and calculates the error between the times. Accordingly, TC (Transmission Convergence) chip in the OLT needs a predictor which predicts the time that the cell will arrive for the current grant. In this paper, we implement the predictor by using shift registers of which the length is equivalent to the equalized round trip delay. As each register consists of 8 bit, OLT can identify which ONU sends what type of cell (ranging cell, user cell, idle cell, and mini-slot). Also, TC chip is designed to calculate the effective bandwidth for all ONUs by using the function of predictor. With the time simulation and the measurement of an implemented optical board, we verify the operation of the predictor.