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2-D DCT/IDCT Processor Design Reducing Adders in DA Architecture  

Jeong Dong-Yun (Magnachip Semiconductor, DDI 3Team)
Seo Hae-Jun (School of Electrical & Electronics Engineering, Chungbuk University)
Bae Hyeon-Deok (School of Electrical & Electronics Engineering, Chungbuk University)
Cho Tae-Won (School of Electrical & Electronics Engineering, Chungbuk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.3, 2006 , pp. 48-58 More about this Journal
Abstract
This paper presents 8x8 two dimensional DCT/IDCT processor of adder-based distributed arithmetic architecture without applying ROM units in conventional memories. To reduce hardware cost in the coefficient matrix of DCT and IDCT, an odd part of the coefficient matrix was shared. The proposed architecture uses only 29 adders to compute coefficient operation in the 2-D DCT/IDCT processor, while 1-D DCT processor consists of 18 adders to compute coefficient operation. This architecture reduced 48.6% more than the number of adders in 8x8 1-D DCT NEDA architecture. Also, this paper proposed a form of new transpose network which is different from the conventional transpose memory block. The proposed transpose network block uses 64 registers with reduction of 18% more than the number of transistors in conventional memory architecture. Also, to improve throughput, eight input data receive eight pixels in every clock cycle and accordingly eight pixels are produced at the outputs.
Keywords
DCT/IDCT; NEDA; Bit-Parallel; Transpose Network;
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Times Cited By KSCI : 3  (Citation Analysis)
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