2-D DCT/IDCT Processor Design Reducing Adders in DA Architecture |
Jeong Dong-Yun
(Magnachip Semiconductor, DDI 3Team)
Seo Hae-Jun (School of Electrical & Electronics Engineering, Chungbuk University) Bae Hyeon-Deok (School of Electrical & Electronics Engineering, Chungbuk University) Cho Tae-Won (School of Electrical & Electronics Engineering, Chungbuk University) |
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